Semiconductor storage device

A storage device and semiconductor technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of complex structure of power supply system, no consideration of data stability, and inability to flexibly deal with discrete transistors of memory cells, etc. The effect of suppressing the increase in the layout area and simplifying the power supply structure

Inactive Publication Date: 2007-05-02
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] However, in the structure shown in this prior art document 1, the operating power supply voltage of the level conversion circuit is supplied from a system different from the power supply voltage of the memory cell, and the voltage level after the level shift is not affected by the threshold value of the memory cell. fixed voltage level of the voltage effect
Even in Patent Document 1, it is necessary to provide a power supply for level shifting in a system different from the memory cell power supply, and the configuration of the power supply system becomes complicated.
In addition, the potential of the selected word line is fixed, and it cannot flexibly cope with the dispersion of the threshold voltage of the memory cell transistor.
[0014] In addition, at the time of data writing, the selected word line is driven to a level higher than the potential of the memory cell power supply, and no consideration is given to the stability of the data of the non-selected memory cells connected to the selected row at the time of data writing.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0156] Fig. 13 is a diagram showing a modified example of the pull-down element according to the second embodiment of the present invention. In the structure shown in FIG. 13, pull-down element PD is constituted by N-channel MOS transistor NQ21 whose gate receives power supply voltage VDD. The drain of this MOS transistor NQ21 is connected to the word line WL, and the source is coupled to the ground node. The word line WL is driven by a word line driver WDV. The word line driver WDV has the same structure as that shown in FIG. 8 .

[0157] In the case of the pull-down element PD shown in FIG. 13 , the gate of the MOS transistor NQ21 receives the power supply voltage VDD, and is normally maintained in an on state to pull down the potential of the word line WL through its channel resistance. Therefore, when the word line is driven to the selected state, the MOS transistor NQ21 is turned on before the potential of the word line WL rises to equal to or higher than the threshold ...

no. 2 example

[0160] 14 is a diagram schematically showing the configuration of a second modified example of the semiconductor memory device according to the second embodiment of the present invention. FIG. 14 shows a case where pull-down element PDa is arranged close to word line driver WDV on word line WL, and pull-down element PDb is arranged far from word line driver WDV from word line WL. Either one of the pull-down elements Pda and PDb is used.

[0161] When the pull-down element PDa is arranged close to the word line driver WDV, the voltage level of the word line WL is set to the voltage level of VDD·Rn / (Rp+Rn) regardless of the wiring resistance Rw1 of the word line. Therefore, the potential of the word line WL can be set according to the value of the on-resistance Rn of the pull-down element PDa.

[0162] On the other hand, when pull-down element PDb is used, assuming that its on-resistance is Rn, voltage VWL1 of word line WL at the end near word line driver WDV is expressed by th...

no. 3 example

[0170] Fig. 15 is a diagram showing the structure of a third modified example of the second embodiment of the present invention. In FIG. 15, a pull-down element PD and a memory cell MC are shown. Pull-down element PD includes a plurality of parallel-connected unit N-channel MOS transistors NU0-NUk. The gates of these N-channel MOS transistors NU0-NUk are connected to the word line WL or commonly receive the power supply voltage VDD. These unit N-channel MOS transistors NU0-NUk have the same threshold voltage conditions as the drive transistors NQ1 and NQ2 of the memory cell MC. That is, the impurity implantation conditions, layout, and dimensions (ratio of channel width W to channel length, W / L) in the channel region are as close as possible to the drive of these unit N-channel MOS transistors NU0-Nuk and memory cells. Transistors NQ1-NQ2 are set identically. Therefore, these drive transistors NQ1 and NQ2 and unit N-channel MOS transistors NU0-NUk are formed by the same man...

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PUM

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Abstract

A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a structure of a static semiconductor memory device capable of stably writing and reading data even under low-voltage operating conditions. Background technique [0002] With the advancement of miniaturization technology, after miniaturization of transistor elements, voltage scaling corresponding to miniaturization is required from the viewpoint of reliability of the elements and power consumption. However, with this miniaturization, the influence of manufacturing parameter fluctuations increases, and the threshold voltage variation of transistors (insulated gate field effect transistors: MOS transistors) constituting the memory cell increases, thereby reducing the operating margin. As a result, it is difficult to write and read data stably even at a low power supply voltage in a semiconductor memory device. [0003] Various proposals have been made for the purpos...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C8/08G11C11/408G11C11/415
Inventor 新居浩二大林茂树塚本康正薮内诚
Owner RENESAS TECH CORP
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