Current-controlled cmos wideband amplifier/equalizer circuit

Abstract

Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier / equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier / equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel). In such an embodiment, each component may have an individual switch to govem its connectivity in the switchable RC network thereby allowing a broad range of amplification and equalization to be performed.

Description

technical field [0001] The present invention relates to communication devices, and more particularly to amplification and equalization techniques applied in said communication devices. Background technique [0002] The development of high-speed circuit technologies such as current-controlled CMOS (or C3MOS) logic has brought significant increases in the speed of circuits fabricated using standard CMOS processing techniques. [0003] In order to adapt the communication system to various input data communication channel types, wideband data amplifiers are required to provide high-pass responses with different amplification levels while providing a smooth frequency response. In another embodiment (US Patent Application Publication No. 20040028158), two separate paths are provided for input data: (1) one with a smooth frequency response (2) the other with a high pass frequency response. After passing through these two paths, the signals are combined at the summing stage. The r...

AI Technical Summary

Problems solved by technology

This will have the undesired and detrimental effect of reducing the bandwidth of the data path

In addition, if this merged input is directly connected to the input of the receiver, due to the additional capacitive load, the impedance matching between the input of the receiver and the PCB (printed circuit board) bonding wire will be severely reduced (that is, the lead to severe impedance mismatch)

This can lead to more undesirable and harmful effects due to the large number of reflections that can greatly reduce the integrity of the input data

Another potential problem with this prior art two-path embodiment 100 is that when signals passing through two different paths are combined in a summer, additional delays can be generated if the two paths have significantly different delays. the jitter

It can be seen that while the prior art two-path embodiment 100 at least provides a solution with adjustable gain and equalizer stages, it has significant limitations

Rather, among all other problems, the prior art two-path embodiment 100 is power-hungry, introduces undesired impedance mismatches, and great care needs to be taken to ensure that the two paths have sufficiently close time delays

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