Method of design of control circuit in static storage in LCD drive chipset
A technology for static memory and driving chips, applied in static indicators, cathode ray tube indicators, instruments, etc., can solve the problems of complex circuit structure and high chip power consumption, reduce chip power consumption, reduce processing time, and reduce line consumption. The effect of the number of scan operations
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[0024] refer to Figure 1~2 In the present invention, the row scan clock CL1 and the MPU system clock MPU_SYS_CLK are used as the basic operation clocks, and each basic operation clock generates two sub-control signals with a pulse width of Ta when its rising edge arrives.
[0025] In order to ensure that the read and write operation of the MPU takes precedence over the row scan operation, the sub-control signal generated by CL1 is output after a delay of Ta. These two sub-control signals represent two time operation areas respectively. When the MPU_PULSE1 signal does not fall between the rising edge of CL1 and the falling edge of CL1_PULSE1, no timing conflict occurs; otherwise, it is determined that a timing conflict occurs. The first sub-control signal CL1_PULSE1 generated by the rising edge of the line scan signal CL1 is used as the operation area of the line scan, and all the control signals required for the line scan are generated in this operation area, and the line ...
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