Semiconductor memory

Abstract

The present invention discloses a semiconductor memory in which a drop in potential of a bit line due to coupling capacitance at the time of data writing can be restored in a space-saving manner without increasing load at the time of reading. The selection circuit selects the complementary bit line in response to the selection signal, and connects the selected complementary bit line to the write data bus or the read data bus. When writing data, the voltage boosting circuit section selects a read data bus to which one of the bit lines of the complementary bit line pair is connected based on the data to be written, and raises the potential of the selected read data bus, wherein The selected bit line is located opposite to the lowered bit line. In this way, the potential level that has been lowered due to the influence of the coupling capacitance between the bit lines can be restored.

Description

technical field [0001] The present invention relates to a semiconductor memory, and more particularly, the present invention relates to a semiconductor memory having a plurality of memory cells arranged in a row and column direction like a matrix and connected between complementary bit lines between. Background technique [0002] Figure 5 A circuit diagram showing an example of memory cells included in a static random access memory (SRAM). [0003] A memory cell 700 in an SRAM includes n-channel metal oxide semiconductor (MOS) field effect transistors (NMOS) 701 and 702 and inverters 703 and 704 between complementary bit lines BL and / BL. One input-output terminal of the NMOS 701 is connected to the bit line BL, and one input-output terminal of the NMOS 702 is connected to the bit line / BL. The other input-output terminal of the NMOS 701 is connected to the input terminal of the inverter 703 , and the other input-output terminal of the NMOS 702 is connected to the output ...

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