A switching I/O node for connection in a multiprocessor computer system

A computer system and output node technology, applied in transmission systems, digital transmission systems, electrical digital data processing, etc., can solve problems such as waiting time

Inactive Publication Date: 2005-03-09
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, transactions originating from or destined for processor 201A may first pass through processor 201B, which may incur the penalty of wasted latency

Method used

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  • A switching I/O node for connection in a multiprocessor computer system
  • A switching I/O node for connection in a multiprocessor computer system
  • A switching I/O node for connection in a multiprocessor computer system

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Embodiment Construction

[0021] While the invention is susceptible to various modifications and alternative forms, specific embodiments of the invention have been described in detail by way of illustration with reference to the drawings. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all that falls within the spirit and spirit of the invention as defined by the appended claims. modifications, equivalents and substitutions within scope.

[0022] Referring now to FIG. 3, a block diagram of a multiprocessor computer system having multiple upstream packet bus links is shown. Multiprocessor computer system 300 includes processors 301A through 301D coupled to I / O node switch device 310 via a pair of I / O packet bus links 315A and 315B, respectively. Processors 301A-301D are coupled together via respective coherent packet bus links 305A-305D. I / O nod...

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Abstract

A switching I / O node for connection in a multiprocessor computer system. An input / output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

Description

technical field [0001] This invention relates to multiprocessor computer system input and output nodes, and more particularly to switching input and output nodes. Background technique [0002] Computer systems using multiple processing units have economical performance scaling capabilities beyond those of currently available single processor based systems. In a multiprocessing environment, rather than centralizing all processing using a single processor, the processing tasks can be divided into groups that are handled by separate processors. The entire processing load is thus distributed among several processors, and this distributed task can be executed in parallel at the same time. Operating system software separates various portions of program code into separate executable programs, and generally assigns a priority level to each program code. [0003] Personal computers (PCs) and other types of computer systems have been designed to share a bus system for processing mem...

Claims

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Application Information

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IPC IPC(8): G06F13/14G06F13/36G06F13/40H04L12/00H04L12/56
CPCG06F13/4022G06F2213/0024G06F2213/0026G06F13/40
Inventor D·E·久利克
Owner ADVANCED MICRO DEVICES INC
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