Semiconductor memory device

Abstract

A semiconductor memory device includes: a device substrate having a semiconductor layer separated by a dielectric layer from a base substrate; a memory cell array having a plurality of memory cells formed and arranged on the semiconductor layer of the device substrate, each the memory cell having a MOS transistor structure with a body in an electrically floating state to store data based on a majority carrier accumulation state of the body; and a sense amplifier circuit configured to read out data of a selected memory cell in the memory cell array to store the read data in a data latch, then transfer the read data to an output circuit and write back the read data into the selected memory cell.

Description

Technical field [0001] The present invention relates to a semiconductor storage device having a memory cell with a transistor / cell structure formed on an SOI substrate. Background technique [0002] Recently, in order to replace the existing DRAM, a semiconductor memory capable of dynamic storage with a simpler cell structure has been proposed (refer to Non-Patent Document 1). The memory cell is composed of one transistor having a floating body (channel body) formed on an SOI substrate. This memory cell sets the state where the excess majority carriers are stored in the main body to the first data state (for example, data "1"), and the state where the excess majority carriers are released from the main body to the second data state ( For example, data "0"), for binary storage. [0003] In the following, this memory cell is called "FBC" (Floating Body Cell), and the semiconductor memory using FBC is called "FBC memory". FBC memory, like normal DRAM, does not use capacitors, the st...

AI Technical Summary

Problems solved by technology

However, the level of the bit line at the time of data reading of the FBC memory must be lowered to suppress impact ionization, so that it is difficult to flow a large cell current, and it is difficult to obtain high detection sensitivity.

If a large cell current cannot flow, it takes time to charge and discharge the bit line connected to the drain of the memory cell, and high-speed reading cannot be performed.

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