Fast clock rearranging method and device with no spike

Abstract

The method includes steps: determining whether clock signal on master-slave board is need to be rearranged; adjusting jumping time of clock selective control signal level to be occurred, and relative relation of jumping time of clock signal level of master-slave board; making the said jumping time of clock selective control signal level be located in time period of identical signal level of clock signal of master-slave board; based on selected jumping time of clock selective control signal level, determining clock signal after clock rearranging. The invention also discloses the device for implementing based on the method. The invention realizes fast clock rearranging with no spike so as to avoid error generated in communication system, raises stability and reliability of communication system.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a fast and glitch-free clock switching method and a device for realizing fast and glitch-free clock switching in a communication system. Background technique [0002] With the increasing development of data communication technology, in order to improve the stability of the entire system in communication equipment, some of the more critical equipment in the system are often backed up. The currently working equipment is the master equipment, and the backup equipment is the slave equipment. When the master device fails, the slave device will be the device in the current working state. This method prevents the failure of the currently working master device from affecting the normal operation of the entire communication system. [0003] The principle of backing up the key communication equipment in the communication system is as attached figure 1 shown. figure 1 It is a func...

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Problems solved by technology

[0017] It can be seen from the above description that because the clock signals of the master and slave switching boards always have a certain phase difference, if the time for the level transition of the clock selection control signal falls within the phase difference of the clock signals of the master and slave switching boards, that is, the clock selection When the time of the level transition of the control signal falls between the rising edges of the two clocks or the time of the level transition of the clock selection control signal falls between the falling edges of the two clocks, the clock signal in the current working state will generate glitches. Glitches can cause bit errors in communication systems

The generation of bit errors reduces the reliability and stability of the communication system, which is not allowed by many communication devices

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