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Coprocessor with multiple logic interface

A technology of coprocessor and protocol processor, applied in the architecture with a single central processing unit, architecture with multiple processing units, electrical digital data processing, etc., can solve problems affecting system performance, etc.

Inactive Publication Date: 2002-04-03
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Latency in processing events that require real-time processing is an issue that directly affects system performance

Method used

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  • Coprocessor with multiple logic interface
  • Coprocessor with multiple logic interface
  • Coprocessor with multiple logic interface

Examples

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Embodiment Construction

[0015] The present invention will be described in terms of an embedded processor complex providing and controlling the programming capabilities of a network processor. A combined implementation typically includes eight main processing units or protocol processor units (PPUs) working with hardware accelerators to support high-speed mode lookup, data manipulation, internal chip management functions, frame parsing, and data Prefetching. Each PPU comprises the following structural components: two CLPs; at least one, and preferably several dedicated and / or shared coprocessor units and an interface between the main processing unit and each coprocessor unit.

[0016] Each coprocessor unit can perform specific network tasks. The main processing unit executes a series of instructions in a stored program. Each co-processor unit is responsive to the main processing unit and adapted to perform specific tasks effectively under the control of the main processing unit. The interface betwe...

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Abstract

An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.

Description

technical field [0001] The present invention relates to the field of network processor systems, and more particularly, to an embedded processor complex comprising one or more protocol processor units (PPU). A plurality of coprocessors associated with the PPU are used in the processor system by interfacing the PPU with the coprocessors to transfer data and instructions among them. Background technique [0002] The use of protocol processor units to provide and control programming capabilities of a network processor is well known. Also, the use of coprocessors with the PPU in designing a computing system to handle complex structures is well established. Delay in processing events that require real-time processing is an issue that directly affects system performance. By assigning a task to a specific coprocessor, rather than asking the PPU to perform the task, the efficiency and performance of a computer system can be improved. It is important for the PPU to communicate with...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/46G06F13/10G06F13/14G06F15/00G06F15/16G06F15/163G06F15/76G06F15/78G06F15/80H04L29/06
CPCG06F15/7864G06F15/16
Inventor 戈登·泰勒·戴维斯马可·C.·海德斯罗斯·博伊德·里文斯马克·安舍尼·里纳尔迪
Owner IBM CORP
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