Dual-control gate semi-floating gate transistor and preparation method thereof

Abstract

The invention provides a dual-control gate semi-floating gate transistor and a preparation method thereof. A shallow doped well region with a U-shaped groove is arranged on a substrate; one part of the floating gate oxide layer covers the side wall and the bottom of the U-shaped groove, the other part of the floating gate oxide layer covers the shallow doped well region on one side of the U-shaped groove, and the floating gate oxide layer covering the shallow doped well region is provided with an opening for exposing the upper surface of the shallow doped well region; the floating gate polycrystalline silicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; the polycrystalline silicon control gate laminated layer comprises a polycrystalline silicon control gate oxide layer positioned on the floating gate polycrystalline silicon layer and a polycrystalline silicon control gate polycrystalline silicon layer positioned on the polycrystalline silicon control gate oxide layer; the metal control gate stack comprises a high-K dielectric layer and a metal gate; the metal control gate stack continuously covers a part of the polycrystalline silicon control gate polycrystalline silicon layer and the shallow doped well region; the upper surface of the metal gate is higher than the upper surface of the polycrystalline silicon layer of the polycrystalline silicon control gate; and the side walls are formed on the side wall of the metal gate and the outer sides of the floating gate stack and the polycrystalline silicon control gate stack.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a dual control gate semi-floating gate transistor and a preparation method thereof. Background technique [0002] As the size of semiconductor devices continues to shrink to 28nm and below process nodes, the thickness of the gate dielectric layer SiON is reduced to less than 2nm, resulting in an increase in the leakage current of the device. The semiconductor industry uses the high-K dielectric material HfO 2 It is necessary to replace SiON as the gate oxide layer to reduce the quantum tunneling effect of the gate dielectric layer, thereby effectively improving the gate leakage current and the power consumption caused by it. [0003] The semi-floating gate transistor is an alternative concept for DRAM devices. Different from the usual 1T1C structure, the semi-floating gate device consists of a floating gate transistor, an embedded tunneling transistor, and a PN junction. T...

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Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a double control gate semi-floating gate transistor and its preparation method, which is used to solve the problem of the gate dielectric layer when charging the floating gate of the semi-floating gate device in the prior art. The problem of large quantum tunneling effect and weak electric field control when the control gate is read

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