Vertical MOSFET device and manufacturing method and application thereof

Abstract

The invention relates to a vertical metal-oxide-semiconductor field effect transistor (MOSFET) device and a manufacturing method and application thereof. The method comprises the following steps: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer which are vertically stacked from bottom to top on a substrate; wherein the molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is greater than the content of germanium in the second germanium-silicon layer; performing etching to form a nano stacked structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming expansion area inner side walls in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming a source electrode and a drain electrode; forming an active region with a shallow trench isolation layer; and removing the false gate to form a gate dielectric layer and a gate electrode. According to the method, the channel size, the size of the inner side wall in the expansion region, the size of the grid electrode and the like can be well controlled, and the method is applicable to nanosheet or nanowire structures.

Description

technical field [0001] The invention relates to the field of transistors, in particular to a vertical MOSFET device and its manufacturing method and application. Background technique [0002] For MOSFETs, it would be particularly desirable to increase the level of integration since it can be an important factor in determining the price of a product. For two-dimensional or planar semiconductor devices, since their degree of integration is mainly determined by the projected area occupied by a unit memory cell on the surface of a silicon wafer, the degree of integration is greatly affected by the level of fine pattern formation technology. However, the extremely expensive process equipment used to increase the pattern fineness will set a practical limit to increase the integration of two-dimensional or planar semiconductor devices. In order to overcome such limitations, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have been...

AI Technical Summary

Problems solved by technology

This is due to the fact that vertical transistors have many challenges in key process modules and process integration

Images