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FPGA life test method

A life test and multiplier technology, applied in the field of FPGA life test, can solve the problems of initial fatal failure and early life failure

Pending Publication Date: 2022-01-28
北京中科胜芯科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If life testing is not carried out, the device containing the defect will show initial fatal failure or early life failure under service conditions

Method used

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  • FPGA life test method

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Embodiment 1

[0022] A kind of FPGA life test method of the present embodiment, carries out following steps:

[0023] 1) Set various configurations of the life test circuit;

[0024] These include the selection of life test circuit configuration mode, the processing method of programmable logic resources, the processing method of embedded multiplier, the processing method of block memory, and the processing method of user IO;

[0025] 2) Set the external excitation conditions required for the test;

[0026] Including, life test voltage, input terminal requirements, output terminal requirements, input signal requirements, amplitude, resistance R, input excitation signal, logic output signal;

[0027] 3) Use the interpolation ring oscillator circuit to measure the junction temperature of the device to realize feedback modification and iterative optimization of the input clock operating frequency, and monitor the status of the device during the life test through the LED status indicator conne...

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Abstract

The invention relates to an FPGA service life test method, and belongs to the technical field of FPGA chip service life test. The method comprises the following steps: 1) setting various configurations of a life test circuit; 2) setting external excitation conditions required by the test; and (3) measuring the junction temperature of the device by using an interpolation ring oscillation circuit so as to realize feedback modification and iterative optimization on the working frequency of an input clock, and monitoring the state of the device in the life test process through an LED state indicator lamp connected with the FPGA so as to ensure that the junction temperature reaches a specified value in the life test process. According to the life test method, temperature test is carried out through a method of interpolating a ring oscillation circuit. After the linear relation between the oscillation frequency and the temperature is established, the corresponding temperature can be obtained only through the output frequency of the ring oscillator.

Description

technical field [0001] The invention relates to an FPGA life test method, which belongs to the technical field of life test of FPGA chips. Background technique [0002] FPGA has the advantages of programmable, high integration, high speed and high reliability. By configuring the logic functions and input / output ports inside the device, the original circuit board-level design is placed in the chip, which improves circuit performance, reduces circuit volume, reduces circuit power consumption, and effectively improves design flexibility. and efficiency. [0003] Through the life test, the devices with inherent defects caused by process defects can be effectively eliminated to ensure that the failure rate of the devices meets the needs of users. If life testing is not performed, a device containing a defect will exhibit incipient fatal failure or early life failure under service conditions. [0004] The life test uses stress to remove from a batch of products those defective ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2855
Inventor 张超刘铮
Owner 北京中科胜芯科技有限公司
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