Low-resource-consumption DICE trigger design method based on commercial technology

Abstract

A low-resource-consumption DICE trigger design method based on a commercial technology starts from a 65nm commercial MOS device SEU generation mechanism under the condition that a chip design process is not affected, node overturning generated by multi-node charge sharing collection is utilized to recover a Recovery effect, anti-SEU reinforcement design is achieved on a physical layout level of a DICE trigger unit, the purposes of low cost, low resource consumption and high reliability are achieved.

Description

technical field [0001] The invention relates to a low-resource consumption DICE flip-flop design method based on a commercial technology, and belongs to the field of CMOS integrated circuit space single event effect protection. Background technique [0002] CMOS integrated circuits are susceptible to single-event upsets and single-event transients in space radiation environments. The generation of SET / SEU is when high-energy ions are incident on the drain region of the off-state MOS transistor, and electron-hole pairs will be generated on its path. Under the action of an electric field, for NMOS, electrons drift to the drain, and for PMOS, holes drift to the drain, thereby generating a transient pulse SET. If there is a reverse positive feedback circuit in the area generated by the SET, and the pulse of SET After the energy is collected by the positive feedback loop and changes the logic state of the feedback loop, SEU will be generated. [0003] The DICE latch is a common...

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Problems solved by technology

[0004] The technical problem solved by the present invention is: Aiming at the current prior art, in ASIC design, the layout design area of ​​the traditional DICE flip-flop is relatively large and the cost is high, a low resource consumption DICE trigger based on commercial technology is proposed device design method

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