N-mode redundancy configuration storage unit circuit for FPGA

Abstract

The invention provides an N-mode redundancy configuration storage unit circuit for an FPGA. The circuit comprises 2N pairs of interlocking storage units, each pair of interlocking storage units comprises a PMOS transistor and an NMOS transistor, the drain electrode of the ith PMOS transistor is connected with the grid electrode of the (i+1)th PMOS transistor, and the drain electrode of the 2Nth PMOS transistor is connected with the grid electrode of the first PMOS transistor; the grid electrode of the ith NMOS is connected with the drain electrode of the (i+1)th NMOS, and the grid electrode of the 2Nth NMOS is connected with the drain electrode of the first NMOS; drain electrodes of the PMOS transistor and the NMOS transistor of each pair of interlocking storage units are connected with each other, and i is greater than or equal to 1 and less than or equal to 2N-1; grid electrodes and source electrodes of the N transmission tubes are respectively connected with each other; and grid electrodes of the N zero clearing tubes are connected with one another. Compared with a two-end read-write storage unit in the prior art, wiring is saved by one time, and wiring and the structure are simplified.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, and relates to an N-mode redundant configuration storage unit circuit for FPGA. Background technique [0002] Since the 1970s, with the development of microelectronics technology, various types of general-purpose programmable logic devices (PLDs) have emerged. Among them, SRAM-based FPGA is widely used. Users can program and configure the storage unit SRAM of the device through software to realize the required logic functions, instead of having to design and manufacture ASIC chips by themselves. FPGA is a kind of high-density complex PLD. It consists of many independent programmable logic blocks, programmable interconnects, and programmable input / output blocks. Connections between logic blocks and with I / O blocks are made through programmable interconnect switches. By downloading the configuration code stream to the configuration storage unit in the chip, the programmable resource...

AI Technical Summary

Problems solved by technology

[0005] That is to say, the prior art has the defects of wiring, complex structure, and cumbersome components.

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