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Metal interconnection structure, preparation method thereof and semiconductor device

A technology of metal interconnection structure and conductive layer, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as poor barrier coverage, reduce short-circuit problems, and achieve good coverage Effect

Pending Publication Date: 2021-10-01
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above problems, the present application provides a metal interconnection structure and its preparation method, and a semiconductor device, which solves the technical problem of poor barrier layer coverage at the turning point of the contact hole of the interconnection structure in the prior art

Method used

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  • Metal interconnection structure, preparation method thereof and semiconductor device
  • Metal interconnection structure, preparation method thereof and semiconductor device
  • Metal interconnection structure, preparation method thereof and semiconductor device

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Embodiment 1

[0049] like figure 1 As shown, the embodiment of the present application provides a metal interconnection structure, including: a substrate 101 , an etching stop layer 102 , a protection layer 103 , a contact hole 104 , a diffusion barrier layer 105 and a conductive layer 106 .

[0050] An etch stop layer 102 is located above the substrate 101 . The etch stop layer 102 is used to prevent over-etching during the etching process of the contact hole 104 , and avoid damage to components under the contact hole 104 caused by over-etching.

[0051] The material of the etch stop layer 102 includes carbon-doped silicon nitride (NDC).

[0052] The etch stop layer 102 includes multi-layer stop layers stacked in sequence along a direction away from the substrate 101 .

[0053] In addition, the etch stop layer 102 also has a blocking function for preventing unwanted elements (eg, copper, tungsten, etc.) from diffusing into the protection layer 103 above it.

[0054] The passivation laye...

Embodiment 2

[0070] like image 3 As shown, the embodiment of the present application provides a metal interconnection structure, including: a substrate 201 , an etch stop layer 202 , an isolation layer 203 , a protection layer 204 , a contact hole 205 , a diffusion barrier layer 206 and a conductive layer 207 .

[0071] The etch stop layer 202 is located above the substrate 201 , and the etch stop layer 202 is used to prevent over-etching during the etching process of the contact hole 205 and avoid damage to components under the contact hole 205 due to over-etching.

[0072] The material of the etch stop layer 202 includes carbon-doped silicon nitride (NDC).

[0073] The etch stop layer 202 includes multi-layer stop layers stacked in sequence along a direction away from the substrate 201 .

[0074] In addition, the etch stop layer 202 also has a blocking function for preventing unnecessary elements (eg, copper, tungsten, etc.) from diffusing into the protective layer 204 above it.

[00...

Embodiment 3

[0096] On the basis of Embodiment 1 or Embodiment 2, this embodiment provides a method for preparing a metal interconnection structure. Figure 5 It is a schematic flowchart of a method for preparing a metal interconnection structure shown in the embodiment of the present application. Figure 6-Figure 8 It is a schematic diagram of a cross-sectional structure formed by related steps of a method for preparing a metal interconnection structure shown in the embodiment of the present application. Below, refer to Figure 5 and Figure 6-Figure 8 The detailed steps of an exemplary method of the method for manufacturing the metal interconnection structure proposed in the embodiment of the present application will be described.

[0097] like Figure 5 As shown, the method for preparing the metal interconnection structure of this embodiment includes the following steps:

[0098] Step S110 : providing a substrate 101 .

[0099] Step S120: if Image 6 As shown, an etch stop layer 1...

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Abstract

The invention provides a metal interconnection structure, a preparation method thereof and a semiconductor device. The metal interconnection structure comprises a substrate, an etching stop layer and a protection layer which are sequentially arranged in a laminated mode, a contact hole penetrating through the protection layer and the etching stop layer, and a diffusion barrier layer, wherein the contact hole comprises a first part and a second part, the first part penetrates through the protection layer and extends into the etching stop layer, and the second part is arranged in the etching stop layer and is connected with the first part of the contact hole; the inclination angle of the side wall of the first part of the contact hole relative to the bottom of the contact hole is smaller than the inclination angle of the side wall of the second part of the contact hole relative to the bottom of the contact hole; and the diffusion barrier layer covers the side wall and the bottom of the contact hole. The connection part of the first part and the second part of the contact hole is located at the etching stop layer, transition is smooth, a sharp angle cannot be formed, the coverage of the diffusion barrier layer is good, and the short circuit problem between the interconnection structures is greatly reduced.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices, in particular to a metal interconnection structure, a preparation method thereof, and a semiconductor device. Background technique [0002] In the back-end process (Back End of Line, BEOL) of semiconductor devices, it is necessary to form several layers of metal interconnection lines and contact plugs between metal interconnection lines of different layers on the semiconductor device layer, so that the semiconductor The electrodes of the device are drawn out. With the continuous shrinking of chip feature size, back-end interconnection technology is becoming more and more important; through-hole tungsten plug deposition is one of the key interconnection technologies. In the technology of 0.25 microns or above, the order of making through-hole tungsten plugs is usually as follows: first form a contact hole on the dielectric layer, and deposit a barrier metal (such as TiN) i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768
CPCH01L23/5283H01L21/76829H01L21/76838H01L23/5226H01L21/76843
Inventor 孔果果周运帆何世伟朱贤士赖建雄夏勇
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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