A 3D stacked fan-out package structure and its manufacturing method

Abstract

The invention discloses a fan-out packaging structure with 3D stacking and back-leading and a manufacturing method thereof. The fan-out packaging structure includes a carrier board (wafer), a chip, a plastic encapsulation layer, a first redistribution layer, a first dielectric layer, a second redistribution layer and a second dielectric layer. The fan-out packaging structure realizes double-sided fan-out, which can effectively reduce the packaging cost and broaden the application range of the structure; this structure mainly relies on the design of the substrate to realize the interconnection of the front and back sides of the chip, rather than based on TSV through holes, which can It effectively reduces the difficulty of the process, and the processing and production can be realized by using general-purpose equipment; in addition, the fan-out packaging structure can shorten the connection distance, which has great advantages in product performance, especially electrical performance and signal transmission, and its loss is smaller. More efficient and faster response times.

Description

technical field [0001] The present invention relates to semiconductor wafer packaging technology, more specifically, to a 3D stacked fan-out package structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, semiconductor devices are becoming more and more complex, and the volume of semiconductor devices is also becoming smaller and smaller. In addition, semiconductor devices are required to have more functions and faster processing speeds. In order to support the increased functions, the semiconductor package including these components has a large number of contact pads for external electrical connection, such as for input or output, these contact pads will greatly increase the surface area of ​​the semiconductor package, and even occupy the semiconductor half of the package surface area. [0003] The traditional wafer-level packaging technology uses fan-in technology (Fan-in), which requires that the chip...

AI Technical Summary

Problems solved by technology

This kind of 2.5D / 3D wafer-level packaging has limited integration, and it is difficult to carry out wafer-level testing in TSV technology. It is difficult to guarantee the yield rate of chips, and the final packaging yield is low, which in turn increases the cost of packaging.

In addition, in the case of stacked package layers, it is difficult to reduce the volume of the stacked package due to the large number of intermediate layers, and this type of package will also increase the volume of the package due to the problem of assembly accuracy.

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