High-precision multichannel synchronous high-speed data acquisition and processing system and method

Abstract

The invention discloses a high-precision multichannel synchronous high-speed data acquisition and processing system and method, and the system comprises a clock distribution calibration source, an ADC data acquisition module, and an ADC data receiving module, an FIFO data caching module, a fractional delay filtering module and a programmable control module in an FPGA, wherein the clock distribution calibration source generates a multi-channel synchronous signal and a synchronous clock, the multi-channel synchronous signal and the synchronous clock are distributed to the ADC data acquisition module for sampling, and the sampled data are sent to the FIFO data caching module through the ADC data receiving module; the programmable control module performs FFT operation according to the sampling data, extracts the phase difference between each channel and the reference channel through a CORDIC algorithm, then calculates the time delay between each channel and the reference channel, and solves the integer and fractional multiple of the sampling period; and the FIFO data caching module and the fractional delay filter sequentially complete integral multiple and fractional multiple movement of a sampling period, and finally a multi-channel synchronization sequence is obtained. According to the invention, high-precision multi-channel synchronous high-speed data acquisition and processing are realized.

Description

technical field [0001] The invention belongs to the technical field of multi-channel signal processing, in particular to a high-precision multi-channel synchronous high-speed data acquisition and processing system and method. Background technique [0002] Multi-channel signal processing technology has a wide range of applications in radar, electronic countermeasures and other fields. With the maturity of microwave technology and signal processing technology, as well as the continuous improvement of high-speed ADC and FPGA device technology, the multi-channel signal processing technology has also proposed higher requirement. For example, the improvement of instantaneous bandwidth inevitably requires a higher sampling rate, and the sampling clock frequency and data output processing speed also need to be improved accordingly; the demand for large dynamic range, as the electromagnetic environment becomes more and more complex, the design of large dynamic The range of the recei...

AI Technical Summary

Problems solved by technology

[0005] In the field of multi-channel signal processing, in order to ensure complete synchronization between channels, although the reference clock line and signal line can be designed with equal lengths in hardware design, there are limitations Due to the limitations of printed board processing technology and design layout and wiring, it is impossible to guarantee that all channels are completely consistent, and in actual work, due to the existence of jitter or disturbance, there will still be differences between channels, so it must be done before signal preprocessing. Synchronize multi-channel acquisition data

At present, multi-channel data acquisition systems are generally synchronized through the following methods: one is to adjust the phase of the sampling reference clock of each channel separately, so as to realize the sampling synchronization between channels. This method can only be applied in some specific occasions, because Its adjustment range is small and can only be adjusted within one clock cycle; second, after the FPGA receives the sampling data from the ADC, it buffers a certain depth through the FIFO, and determines the data in the FIFO by calculating the phase difference between each channel and the reference channel. This method is flexible and convenient, and does not require too much hardware support. It only needs to perform simple phase difference calculation in FPGA, and it has been widely used in multi-channel signal processing. However, this method can only achieve the synchronization of integer multiples of the sampling period, and it is not suitable for applications with high synchronization requirements.

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