Bidirectional voltage-stabilizing electrostatic surge full-chip protection integrated circuit

A bidirectional voltage regulation, integrated circuit technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of large chip area and low protection efficiency, and achieve the effect of improving robustness

Pending Publication Date: 2021-03-26
钳芯半导体科技(无锡)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the deficiencies in the background technology, the present invention provides a two-way voltage stabilizing electrostatic surge full-chip protection integrated circuit. The technical problem to be solved is that the chip area occupied by the device in the existing one-way ESD protection application is too large and the protection efficiency is low. However, it cannot provide full-mode EOS / ESD protection functions for I / O terminals, power supplies, or hot-swap interfaces of ICs and board-level circuits.

Method used

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  • Bidirectional voltage-stabilizing electrostatic surge full-chip protection integrated circuit

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Effect test

Embodiment 1

[0032] Such as figure 1As shown, a bidirectional voltage stabilized electrostatic surge full-chip protection integrated circuit includes a P-type substrate 101, and the upper surface of the P-type substrate 101 is respectively provided with a first P well 103, a first N well 102 and a second N well. Well 105, the left side of the first P well 103 is connected to the right side of the first N well 102, the left side of the first N well 102 is flush with the left side of the P-type substrate 101, the first N well 102 is provided with a first P+ implantation region 106, and the right side of the first P+ implantation region 106 is provided with a first N+ implantation region 107 at intervals, and the first N+ implantation region 107 is respectively on the first N well 102 and the first P well 103 ;

[0033] The right side of the first P well 103 is connected to the left side of the second N well 105, the right side of the second N well 105 is flush with the right side of the P-t...

Embodiment 2

[0052] Such as Figure 5 As shown, in this embodiment, the P-type substrate 101, the first P well 103, the first N well 102, the second N well 105, the first P+ implantation region 106, the first N+ implantation region 107, and the fifth P+ implantation region 113 , the structural relationship between the third N+ implantation region 112 and the second P+ implantation ring 108 refers to Embodiment 1.

[0053] Specifically, the third P well 103 is respectively provided with a third N well 104 and a first N+ injection ring 301 in the second P+ injection ring 108, and the first N+ injection ring 301 is respectively provided in the third N well 104 and the first P well 103, the third N well 104 is provided with a sixth P+ implantation region 302 in the first N+ implantation ring 301, the distance between the left side of the sixth P+ implantation region 302 and the first N+ implantation ring 301 and the sixth P+ implantation region The distance between the right side of 302 and t...

Embodiment 3

[0056] Such as Figure 6 As shown, in this embodiment, the P-type substrate 101, the first P well 103, the first N well 102, the second N well 105, the first P+ implantation region 106, the first N+ implantation region 107, and the fifth P+ implantation region 113 , the structural relationship between the third N+ implantation region 112 and the second P+ implantation ring 108 refers to Embodiment 1.

[0057] Specifically, the third P well 103 is provided with a third N well 104 in the second P+ implantation ring 108, and the third N well 104 is provided with a Japanese-shaped fourth N+ implantation region in the second P+ implantation ring 108 along the lateral direction. 401, the four sides of the fourth N+ implantation region 401 are respectively on the third P well 103 and the third N well 104, the left N+ ring and the right N+ ring of the fourth N+ implantation region 401 are arranged symmetrically, and the third N well 104 is on A seventh P+ implantation region 402 is a...

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PUM

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Abstract

The invention relates to the field of electrostatic discharge protection and surge resistance of integrated circuits, and discloses a bidirectional voltage-stabilizing electrostatic surge full-chip protection integrated circuit. The structural center of the circuit is symmetrically set. In actual use, current discharge paths in six working modes of PS, PD, NS, ND, DS and SD are completely identical in two directions and have Zener diode auxiliary SCR trigger characteristics, in addition, symmetrical forward and reverse EOS / ESD protection characteristics are achieved between any two ports of I / O, VSS and VDD, the chip design area and parasitic capacitance can be reduced, the on-resistance is reduced, and the EOS / ESD robustness is enhanced.

Description

technical field [0001] The invention relates to the field of electrostatic discharge protection and anti-surge of integrated circuits, in particular to a two-way voltage stabilizing electrostatic surge full-chip protection integrated circuit. Background technique [0002] During the use of electronic products, electrostatic discharge or surge is the main reason for their failure. With the development of integrated circuits in the direction of ultra-deep submicron and nanometer according to the law of scaling, the gate oxide of devices is getting thinner and the channel length is getting shorter and shorter, and integrated circuits are becoming more and more sensitive to static electricity and surge damage. According to the analysis and statistics of the failure mechanism of electronic products, the failure of more than half of electronic components is caused by surge (EOS) and electrostatic discharge (ESD). Especially with the continuous development of integrated circuit ma...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0255H01L27/0259H01L27/0296
Inventor 梁海莲马琴玲顾晓峰
Owner 钳芯半导体科技(无锡)有限公司
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