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Method for covalently grafting fluorine-free nano-pore low k dielectric film on surface of semiconductor

A surface covalent, dielectric thin film technology, applied in nanotechnology for materials and surface science, semiconductor/solid-state device manufacturing, nanotechnology, etc., can solve problems such as the inability to achieve low dielectric constant, and prevent strong corrosion. Function, composition controllable, thickness controllable effect

Active Publication Date: 2021-01-08
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] CN201910087448 provides a method for preparing self-crosslinking organic polymers on semiconductor surfaces; films can be grafted on semiconductor surfaces, but the performance of low dielectric constant cannot be achieved

Method used

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  • Method for covalently grafting fluorine-free nano-pore low k dielectric film on surface of semiconductor
  • Method for covalently grafting fluorine-free nano-pore low k dielectric film on surface of semiconductor
  • Method for covalently grafting fluorine-free nano-pore low k dielectric film on surface of semiconductor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] This embodiment relates to a method for covalently grafting a low k dielectric film on the surface of a semiconductor based on diazonium salt technology. The semiconductor substrate can be silicon, germanium, or gallium arsenide (specifically, silicon is selected as the substrate in this embodiment), specifically The implementation steps are as follows:

[0047] Step (1): Under the condition of a temperature of 20° C., the semiconductor substrate is ultrasonically cleaned sequentially with acetone, alcohol and deionized water, and the cleaning time is 5 minutes each time;

[0048] Step (2): Place the cleaned semiconductor substrate in a 3v% HF solution at a temperature of 20°C for 1 min;

[0049] Step (3): At a temperature of 20°C, immerse the corroded semiconductor surface directly into the prepared chemical solution ① for surface passivation. The immersion time is 30s, so that the semiconductor surface is transformed into a passivation layer surface, thereby preventin...

Embodiment 2

[0058] This embodiment relates to a method for covalently grafting a low k dielectric film on a semiconductor surface based on diazonium salt technology. The semiconductor substrate is silicon, and the specific implementation steps are as follows:

[0059] Step (1): Under the condition of a temperature of 20° C., the semiconductor substrate is ultrasonically cleaned sequentially with acetone, alcohol and deionized water, and the cleaning time is 5 minutes each time;

[0060] Step (2): Place the cleaned semiconductor substrate in a 0.5v% HF solution at a temperature of 20°C for 10 minutes;

[0061] Step (3): At a temperature of 20°C, directly immerse the corroded semiconductor surface in the prepared chemical solution ① for surface passivation. The immersion time is 30s, so that the semiconductor surface is transformed into a passivation layer surface, thereby preventing The surface is oxidized in the next reaction;

[0062] The configuration process of the chemical solution ①...

Embodiment 3

[0067] This embodiment relates to a method for covalently grafting a low k dielectric film on a semiconductor surface based on diazonium salt technology. The semiconductor substrate is silicon, and the specific implementation steps are as follows:

[0068] Step (1): Under the condition of a temperature of 20° C., the semiconductor substrate is ultrasonically cleaned sequentially with acetone, alcohol and deionized water, and the cleaning time is 5 minutes each time;

[0069] Step (2): at a temperature of 20°C, place the cleaned semiconductor substrate in a 5% volume fraction of HF solution, and soak for 1 min;

[0070] Step (3): At a temperature of 20°C, immerse the corroded semiconductor surface directly in the prepared chemical solution ① for surface passivation. The passivated semiconductor surface is oxidized in the next reaction;

[0071] The configuration process of the chemical solution ① is as follows: add 100ml deionized water to the Teflon beaker, then add 0.2g sodi...

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Abstract

The invention discloses a method for covalently grafting a fluorine-free nano-pore low k dielectric film on the surface of a semiconductor. The method comprises the steps of: chemically grafting a passivation layer to the surface of a semiconductor through the diazonium salt technology in the atmospheric environment, wherein the component of the passivation layer is an organic polymer of diazoniumsalt, the thickness of the passivation layer is controllable, and the passivation layer aims to prevent the SiH surface from being oxidized and serve as an intermediate layer for grafting a low k film at the same time; and electrically grafting a low k layer with a POSS cage structure on the surface by using a diazonium salt technology in an atmospheric environment. The dielectric constant valueof the film prepared by the method is 2.1-2.2, and the dielectric constant of the film is remarkably reduced compared with that of previous researches. The method can be completely carried out in an atmospheric environment, inert gas atmosphere protection is not needed, any soluble vinyl monomer can be grafted, F ions can be prevented from corroding the monomer and damaging some covalent bonds, and the dielectric film obtained by adopting the method has excellent comprehensive properties such as dielectric properties and hardness.

Description

technical field [0001] The invention relates to the technical field of covalently grafting organic insulating films on the surface of semiconductors and low k materials, and relates to a method for covalently grafting low dielectric constant (low k) dielectric films on the surface of semiconductors, in particular to a method for covalently grafting low k dielectric films on the surface of semiconductors. A method for grafting fluorine-free nanoscale porous low k dielectric films. Background technique [0002] As a key technology in the production of ultralarge scale integration (ULSI), multilayer interconnection technology has made great progress in recent years. With the continuous miniaturization of electronic devices in VLSI, the transmission delay caused by interconnection increases rapidly. In order to meet the high-speed information transmission requirements of 6G communication in the future, it is urgent to reduce the resistance-capacitance (RC) delay between interco...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02B82Y30/00
CPCH01L21/02203H01L21/02118H01L21/02282B82Y30/00
Inventor 曹亮亮吴蕴雯李明
Owner SHANGHAI JIAO TONG UNIV
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