Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method. The forming method comprises the steps of providing a base, wherein the base comprises a substrate, a gate structure located onthe substrate, an insulating cap layer located on the gate structure, and a source-drain connecting layer located on the substrate between the gate structures, wherein the top surface of the source-drain connecting layer is lower than the top surface of the insulating cap layer; forming an etching stop layer on the insulating cap layer; forming a source-drain dielectric layer on the source-drain connecting layer; removing the source-drain dielectric layer on the source-drain connecting layer by adopting a first etching process to form a first opening, wherein in the first etching process, theetched rate of the insulating cap layer is less than the etched rate of the source-drain dielectric layer, and the etched rate of the etching stop layer is less than the etched rate of the insulatingcap layer; and forming a source-drain contact hole plug in the first opening. In the process of forming the first opening, the etching stop layer is not easy to etch and remove, the probability of bridging between the source-drain contact hole plug and the gate structure is reduced, and the electrical performance of the semiconductor structure is optimized.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The inte...

AI Technical Summary

Problems solved by technology

In order to improve integration and reduce costs, the critical dimensions of components are continuously reduced, and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.

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