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Chip package structure and manufacturing method thereof

A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as uneven force, electrical bonding failure, and poor reliability of chip packaging structure. Achieve the effect of improving reliability, reducing uneven force, and reducing the possible effect of electrical joint failure

Pending Publication Date: 2020-09-22
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Generally speaking, when a traditional chip is bonded to a substrate, such as flip chip mounting, since the chip joint is often located in the center of the chip, there is no support on both sides of the chip, and it is easy to damage the chip due to uneven force during bonding. Tilt, causing poor electrical connection
In addition, since the stress is concentrated at the junction, it is easy to break at the junction, causing the possibility of electrical junction failure
The above problems will make the reliability of the chip packaging structure worse. Therefore, how to improve the reliability of the chip packaging structure will become an important subject

Method used

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  • Chip package structure and manufacturing method thereof
  • Chip package structure and manufacturing method thereof
  • Chip package structure and manufacturing method thereof

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Embodiment Construction

[0033] Figure 1A to Figure 1D It is a schematic cross-sectional view of a manufacturing process of a chip packaging structure 100 according to an embodiment of the present invention. Please refer to Figure 1A Firstly, a circuit substrate 110 and a chip 120 are provided. In detail, the circuit substrate has a plurality of pads 112 and a solder resist layer 114 . The solder resist layer 114 covers the conductive circuit (not shown) in the circuit substrate 110 and exposes a plurality of pads 112 , so as to facilitate subsequent electrical connection of the pads 112 . The chip 120 has an active surface 120a. The chip 120 is, for example, a memory chip, a microprocessor chip or an Application Specific Integrated Circuit (ASIC). However, the present invention does not limit the type of the chip 120 , which can be determined according to actual design requirements.

[0034] Please continue to refer Figure 1A , the circuit substrate 110 is formed with a two-stage thermosetting...

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Abstract

A manufacturing method of a chip package structure is provided. A circuit substrate and a chip are provided. The circuit substrate is formed with a two-stage thermosetting adhesive layer. An active surface of the chip is formed with a conductive pillar and a support pillar. The circuit substrate is passed through the two-stage thermosetting adhesive layer to abut the active surface of the chip. The two-stage thermosetting adhesive layer is dropped between the conductive pillar and the support pillar. A bonding process is performed, and the chip is electrically connected to the circuit substrate through the conductive pillar and supported by the support pillar to be positioned on the circuit substrate. The two-stage thermosetting adhesive layer is fully cured. An encapsulant is formed on the circuit substrate to encapsulate the chip, the conductive pillar, the support pillar and the two-stage thermosetting adhesive layer. A chip package structure is also provided.

Description

technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] Generally speaking, when a traditional chip is bonded to a substrate, such as flip chip mounting, since the chip joint is often located in the center of the chip, there is no support on both sides of the chip, and it is easy to damage the chip due to uneven force during bonding. tilted, resulting in poor electrical connection. In addition, since the stress is concentrated on the joint, it is easy to cause fracture at the joint, which may lead to the possibility of electrical joint failure. The above-mentioned problems will deteriorate the reliability of the chip packaging structure. Therefore, how to improve the reliability of the chip packaging structure will become an important subject. Contents of the invention [0003] The invention provides a chip packag...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L23/488H01L23/24
CPCH01L23/24H01L24/16H01L24/32H01L24/81H01L24/83H01L2224/16225H01L2224/32225H01L2224/81007H01L2224/83009H01L2224/73204H01L2924/00
Inventor 黄东鸿黄国樑
Owner CHIPMOS TECH INC
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