Configurable convolutional neural network processor circuit

Abstract

The invention provides a configurable convolutional neural network processor circuit, which comprises an FIR filtering module, a windowing processing module and a neural network operation module, wherein the neural network operation module comprises a convolution layer, a pooling layer, a configurable activation function layer and a full connection layer; and the configurable activation function layer comprises an absolute value setting module, an interval judgment module, a first multiplexer, a configuration module, an address generation module, an RAM, an interval expansion module and a second multiplexer. The configurable activation function layer is configured with a sigmoid function or a tanh function and errors, so that the universality and the flexibility of the processor are greatly improved; by combining hierarchical quantization and saturation truncation, the quantization standard of each layer of neural network is configurable, and the overflow risk is reduced; and an FIR filtering function is realized by multiplexing a multiply-accumulate-add operation unit of a full connection layer, and data is transmitted by adopting a two-stage data transmission mode, so that the power consumption is further reduced.

Description

technical field [0001] The invention belongs to the technical field of artificial intelligence, and in particular relates to a configurable convolutional neural network processor circuit. Background technique [0002] Artificial Intelligence (AI) is a strategic industry leading the future, and AI chips, as a key technical link in the entire field of artificial intelligence, are the foundation of my country's artificial intelligence industry and an important hurdle to achieve breakthroughs in artificial intelligence. As an important way to develop artificial intelligence, deep learning differs from traditional computing models in that it does not require large-scale logic programming, but requires massive parallel computing. New computing models and the strong demand for new computing in the era of artificial intelligence are giving birth to new Dedicated computing chips. The maturity of deep learning algorithms, the improvement of computing power and big data jointly promot...

AI Technical Summary

Problems solved by technology

However, the way the CPU implements the deep convolutional neural network cannot make good use of the parallelism characteristics of the convolutional neural network algorithm, so it cannot meet the low latency and low power consumption requirements required by most applications.

Although the convolutional neural network on the GPU can make good use of the parallelism of the convolutional neural network algorithm to achieve good performance, its high power consumption cannot meet the requirements of portable devices

Traditional ASIC (Application Specific Integrated Circuit, ASIC) special artificial intelligence calculation acceleration circuit, for a specific algorithm, realizes calculation through a dedicated circuit structure, but its configurability is poor, and it cannot keep up with the rapid development of artificial intelligence algorithms

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