Multi-node SRIO communication design method and device based on ZYNQ

Abstract

The invention discloses a multi-node SRIO communication design method based on ZYNQ, and the method comprises the steps: S1, enabling a PL to process request and request protocol packages to obtain the protocol type of data, and giving an indication mark; s2, classifying and caching the user interface data according to the indication sign, putting each complete frame into a cache queue, and judging a queue space; s3, the PS receives the data and sends the data; s4, in the data receiving and sending operation process of the PS, the PL performs multi-node data processing to obtain different datasending completion interruptions or receiving completion interruptions and sends the data sending completion interruptions or receiving completion interruptions to the PS, and various data query registers are provided; s5, the PS reads the corresponding data according to the received data sending completion interruption or receiving completion interruption, clears the interruption after the reading operation is completed, inquires whether residual instructions are executed or not, and returns to the step S1; not only is multi-node communication satisfied, but also flexible processing of an application layer is satisfied.

Description

technical field [0001] The invention relates to the field of electronic communication, in particular to a ZYNQ-based multi-node SRIO communication design method. Background technique [0002] In the field of high-speed AD, high-speed ADC acquisition or high-speed GTX / GTH for data transmission is required, and there is a demand for SRIO communication and data transmission, while DSP and other devices cannot meet the needs of ADC acquisition, etc. FPGAs are needed for implementation, but the existing FPGA-based Most of the SRIO communication is a single point for communication or data transmission, and the FPGA that uses multiple nodes for communication or transmission cannot transplant the SRIO processing application of the traditional DSP. [0003] The Serial RapidIO Gen2 IP core provided by FPGA implements protocols below the application layer, but does not provide multi-node control applications. Therefore, FPGA-based SRIO communication is currently limited by node control...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is that FPGA-based multi-node communication lacks flexibility when high-speed ADC acquisition or high-speed GTX / GTH data transmission is required, and there is a need for SRIO communication and data transmission. ZYNQ's multi-node SRIO communication design method solves the above problems

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