A hardware accelerator system for finite-difference time domain method and its implementation method

Abstract

The present invention discloses a time-domain finite difference method hardware accelerator system and its realization method. The system includes an arrangement structure of chain calculation processing units, multiple sets of storage blocks and excitation source evaluators; the arrangement structure of the chain calculation processing units is as follows: A combination of a plurality of PEs arranged along a one-dimensional direction is used to calculate the electric field value and / or magnetic field value of a three-dimensional grid point for electromagnetic field simulation; the storage block is composed of a plurality of block random access memories for storing the The electric field value and / or magnetic field value of the grid point obtained by PE calculation; the excitation source evaluator is used to assign the electric field value and / or magnetic field value stored in the storage block. The invention can improve the utilization rate of PE, reduce the wiring difficulty and delay of comprehensive realization on FPGA, increase the bandwidth capacity of off-chip storage, and improve the expandability and grid adaptability of PE array. The invention can be applied to the field of hardware accelerators based on FPGA platform.

Description

technical field [0001] The invention relates to the field of a hardware accelerator based on an FPGA platform, in particular to a time domain finite difference method hardware accelerator system and an implementation method thereof. Background technique [0002] When the existing FDT hardware accelerator based on the FPGA (Field Programmable Gate Array) platform calculates the electromagnetic field in three-dimensional space, the large grid that needs to be simulated will be calculated according to the logic resources and storage resources on the FPGA. Evenly divided into several small grids, and each small grid is allocated a computing processing unit PE (Processing Element) and a set of block random access memory BRAM (Block RAM) for storing data, forming a three-dimensional array of small grids . Each calculation processing unit PE is responsible for calculating the electric field value and magnetic field value of all grid points in the small grid, and updating the value...

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Problems solved by technology

This defect will cause different projects to be simulated each time, and the bit stream of the FPGA needs to be reprogrammed to configure the hardware accelerators of different systems. The amount of engineering is very large, and it is difficult to be practical in actual projects.

That is, the scalability and grid adaptability of the PE array are very weak

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