Signal jitter estimation method for output end of LPDDR4 IO interface

An LPDDR4IO, output technology, applied in the direction of calculation, design optimization/simulation, CAD numerical modeling, etc., to achieve the effect of shortening time-consuming, high accuracy, and enriching frequency domain details

Active Publication Date: 2020-05-08
XIDIAN UNIV
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Problems solved by technology

[0009] The purpose of the present invention is to address the above-mentioned deficiencies in the prior art, and propose a signal jitter estimation method for the output of the LPDDR4 IO interface for the signal jitter caused by the noise of the power supply rail, and solve how to use the numerical calculation method to quickly and accurately LPDDR4 The problem of jitter estimation caused by power supply noise in the IO link can be applied in actual engineering

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  • Signal jitter estimation method for output end of LPDDR4 IO interface
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  • Signal jitter estimation method for output end of LPDDR4 IO interface

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[0055] The present invention will be further described below in conjunction with the accompanying drawings.

[0056] Refer to attached figure 1 , to further describe the specific steps of the present invention.

[0057] Step 1, obtaining the actual working parameters of the MOS tube.

[0058] The first step is to extract the working data of the output device used in the actual LPDDR4 IO interface link, and draw the current and voltage working curves of the pull-up NMOS and the pull-down NMOS.

[0059] The second step is to obtain the DC operating point voltage V of the pull-up NMOS transistor according to the current-voltage curve of the pull-up NMOS. 0 , DC transconductance g dc and small signal AC transconductance g m .

[0060] Specific steps are as follows:

[0061] In the first step, the center point of the maximum and minimum values ​​of the gate-source voltage when the pull-up NMOS is working is taken as the DC operating point voltage V 0 .

[0062] Step 2, find...

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Abstract

A signal jitter estimation method for an output end of an LPDDR4 IO interface mainly solves the problem that in the prior art, for an LPDDR4 IO interface adopting a double-NMOS structure, a simple numerical calculation method for estimating signal time sequence jitter caused by power supply track noise does not exist. The method comprises the following steps: (1) obtaining actual working parameters of an MOS transistor; (2) obtaining equivalent model parameters of link interconnection; (3) generating a transmission function for estimating jitter of the output end during pull-up; (4) generatinga transmission function for estimating the jitter of the output end during pull-down; (5) obtaining a ground orbit noise spectrum when the interface link works; and (6) generating a jitter estimationvalue of the LPDDR4 IO interface link. Compared with a software simulation method, a numerical calculation method adopted in the invention takes a short time than, and makes the generated transmission function have rich frequency domain details.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and further relates to an IO interface (Input) for the fourth-generation low-power double-rate synchronous dynamic random access memory LPDDR4 (Low-power double data ratefourth generation) in high-speed circuit signal analysis technology / Output Interface) output signal jitter estimation method. The invention can be used for estimating timing jitter in the process of high-speed circuit data transmission and participates in the design of power supply distribution network for suppressing power supply track noise. Background technique [0002] The timing jitter of a digital signal refers to the deviation between the actual signal edge time and the ideal edge time position. Excessive deviation will distort the signal level sampled by the receiver and generate bit errors. The noise sources that cause deterministic timing jitter mainly include crosstalk, power supply rail noise, rising edg...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/20G06F111/10G06F17/15
CPCG06F17/15G06F17/156
Inventor 刘洋夏铭泽曾操孙肖扬朱磊磊
Owner XIDIAN UNIV
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