Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. A second trench extending along a second direction is formed in a semiconductor substrate. U-shaped fins are arranged onthe two sides of the second trench in a staggered mode. The U-shaped fin is provided with a first trench extending along a first direction. The first source / drain regions are formed in the fins at the tops of the two sides of the first trench; a second source / drain region is formed in the fin at the bottom of the first trench; a gate line is filled in the first trench and extends along the firstdirection; the embedded wire is filled in the second trench extending along the second direction, so that the two first source / drain regions in the U-shaped fin respectively form double vertical L-shaped channels with the second source / drain region, the effective channel length is favorably increased, the short channel effect is overcome, and the smaller feature size and the higher integration degree are further favorably realized; and the U-shaped fins on the two sides of the second trench are arranged in a staggered manner, so that the coupling effect between adjacent active regions can be improved, and the device performance can be improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] A vertical surrounding gate transistor (SGT) with a buried bit line, which uses increased isolation rules to greatly reduce the difficulty of shallow trench isolation manufacturing, and its process includes lengthy buried bit lines The process steps, the process steps of the spin-on dielectric layer (SOD), the process steps of metal and N-type doped polysilicon to define the gate length of the transistor, the process is complicated, and the stability of the threshold voltage of the memory array is also significantly reduced. , and under the limitation of the vertical size, it is impossible to reduce the change of the threshold voltage (Vth) with a longer channel length. [0003] In addition, due to the continuous miniaturization of the size of semiconductor devices, th...

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Problems solved by technology

[0002] A vertical surrounding gate transistor (SGT) with a buried bit line, which uses increased isolation rules to greatly reduce the difficulty of shallow trench isolation manufacturing, and its process includes lengthy buried bit lines The process steps, the process steps of the spin-on dielectric layer (SOD), the process steps of metal and N-type doped polysilicon to define the gate length of the transistor, the process is complicated, and the stability of the threshold voltage of the memory array is also significantly reduced. , and under the limitation of the vertical size, it is impossible to reduce the change of the threshold voltage (Vth) with a longer channel length

[0003] In addition, due to the continuous miniaturization of the size of semiconductor devices, the distance between the memory cells of the dynamic random access memory (DRAM) is also closer, which often leads to a very strong word line-word line coupling effect (word line-word line-coupling effect). word line coupling), which will affect device performance and reliability, and even cause DRAM data access errors

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