Integrated circuit clock tree comprehensive optimization method

Abstract

The invention relates to the technical field of integrated circuit design industry automation (EDA), and provides an integrated circuit clock tree comprehensive optimization method, which comprises the following steps of S1, presetting parameters in a clock tree constraint file; s2, automatically generating a line layout according to the parameters; s3, adjusting the positions of registers in thecircuit layout to enable the difference value between the clock source and the wiring length of each register to be within a preset range; s4, arranging a plurality of driving units at the clock signal source, wherein the driving units are used for driving loads of the clock tree; and S5, replacing the driving units to enable the driving capacities of the driving units to be the same. Through thedesign, the most important clock tree comprehensive design link in the integrated circuit rear-end design process is subjected to design sequence standardization, so that the clock tree comprehensivedesign link has good universality, the design threshold of the rear-end link is reduced, the labor cost is reduced, the design efficiency is improved, and the design quality is ensured.

Description

technical field [0001] The invention relates to the technical field of automated EDA in the integrated circuit design industry, in particular to a comprehensive optimization method for an integrated circuit clock tree. Background technique [0002] The current rapid development of Moore's Law makes it possible to integrate hundreds of millions of transistors on a single semiconductor chip. The sharp increase in semiconductor integration density has also brought great challenges to the design structure of digital circuits. [0003] The clock tree structure is initially generated by an electronic design automation (EDA) software system, which transmits clock signals from clock signal sources to other clock sinks by using a clock network consisting of fan-out buffers or fan-out inverters. A clock tree can vary the number of buffers or inverters and send the clock signal to the clock receivers, usually depending on the number of clock receivers that need to receive the clock si...

AI Technical Summary

Problems solved by technology

However, this method of automatically generating integrated circuit layout lines through software is firstly based on computer algorithms and previous experience. For innovative integrated circuits, copying this method may not be effective; secondly, when automatically generating integrated circuit layouts After the route, there are many ways to analyze and adjust the route, most of which are based on personal experience, and it is difficult for novices to learn the essence of it

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