Method for manufacturing memory device and memory device

Abstract

The present application discloses a manufacturing method of a memory device and the memory device, including: providing a substrate, the substrate including a memory cell area and a peripheral circuit area; performing ion implantation on the active area of ​​the memory cell area; Deposit an isolation layer, the innermost layer of the isolation layer includes a silicon oxide layer, and the outermost layer of the isolation layer includes a silicon nitride layer; the isolation layer is etched until the silicon oxide layer on the substrate plane is exposed; the peripheral circuit Ion implantation is performed at the source end of the area; a silicon oxide layer is deposited on the substrate so that the pattern on the substrate is covered by the silicon oxide layer; the silicon oxide layer in the memory cell area is removed; the outermost layer of the memory cell area is removed by a wet etching process A silicon nitride layer; performing ion implantation on the drain end of the storage region. The present application can thin the sidewall of the gate without thinning the sidewall of the peripheral circuit, and then meet the thickness of the sidewall of the peripheral circuit on the basis of ensuring the ILD filling yield to increase the breakdown voltage window.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a storage device and the storage device. Background technique [0002] The market share of non-volatile memory (NVM) devices is getting higher and higher. NVM devices are usually divided into two types: stack gate memory devices and split gate memory devices. split gate memory device. [0003] Traditional split-gate memory devices use asymmetric source-drain structures. In order to meet the market demand for high density, high performance and low cost, the technology nodes are getting smaller and smaller, and the corresponding drain size is also reduced to less than 50 nanometers. Therefore, The requirements for the sidewall process and the inter layer dielectric (ILD) filling process are getting higher and higher. [0004] In the process steps of forming the sidewall of the NOR type split gate memory device below th...

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Problems solved by technology

[0010] The present application provides a method for manufacturing a memory device and a memory device, which can solve the problem of poor ILD filling caused by the narrow drain end of the memory cell region in the method for manufacturing a memory device provided in the related art

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