Manufacturing method of memory device and memory device

Abstract

The invention discloses a manufacturing method of a memory device and the memory device. The method comprises the steps: a substrate is provided, wherein the substrate comprises a memory cell region and a peripheral circuit region; ion implantation is carried out on the active region of the memory cell region; an isolation layer is deposited on the substrate, the innermost layer of the isolation layer comprises a silicon oxide layer, and the outermost layer of the isolation layer comprises a silicon nitride layer; the isolation layer is etched until the silicon oxide layer on the substrate plane is exposed outside; ion implantation is carried out on the source end of the peripheral circuit region; a silicon oxide layer is deposited on the substrate to enable the pattern on the substrate tobe covered by the silicon oxide layer; the silicon oxide layer in the memory cell area is removed; the silicon nitride layer on the outermost layer of the memory cell region is removed through a wetetching process; and ion implantation is carried out on the drain end of the memory region. The side wall of the peripheral circuit is not thinned while the side wall of the gate is thinned, so that the thickness of the side wall of the peripheral circuit is satisfied on the basis of ensuring the ILD filling yield so as to improve the breakdown voltage window.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a storage device and the storage device. Background technique [0002] The market share of non-volatile memory (NVM) devices is increasing. NVM devices are generally divided into two types: stack gate (stack gate) memory devices and split gate (split gate) memory devices. split-gate memory devices. [0003] Traditional split-gate memory devices adopt an asymmetric source-drain structure. In order to meet the market demand for high density, high performance, and low cost, technology nodes are getting smaller and smaller, and the corresponding drain size is also reduced to less than 50 nanometers. Therefore, The requirements for the sidewall process and the filling process of the dielectric layer (inter layer dielectric, ILD) are getting higher and higher. [0004] In the process steps of forming sidewalls of NOR type s...

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Problems solved by technology

[0010] The present application provides a method for manufacturing a memory device and a memory device, which can solve the problem of poor ILD filling caused by the narrow drain end of the memory cell region in the method for manufacturing a memory device provided in the related art

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