A Configurable Hybrid Heterogeneous Computing Core System for Multi-Domain Chip Design

Abstract

A configurable hybrid heterogeneous computing core architecture for multi-domain chip design, including: a workload scheduling module and a processing engine, the processing engine includes a thread group scheduling module and a specific domain computing unit; the workload is sent by the driver to the workload scheduling Module, and then sent to the thread group scheduling module, the thread group scheduling module splits the workload into several thread groups and sends each thread group to the specific domain computing unit of the specified application for execution; the specific domain computing unit includes CU controller, register Files, domain-specific cores, and L1 cache; the CU controller is used to read shaders and decode instructions, and then send instructions to each domain-specific core for execution. A set of register files in each domain-specific computing unit shares L1 with domain-specific cores cache. The invention uses the computing unit in a specific field as a building block, which can shorten the project design time and quickly and efficiently create products required by the market.

Description

technical field [0001] The invention belongs to the field of hardware and chip architecture design, in particular to a configurable hybrid heterogeneous computing core system for multi-field chip design. Background technique [0002] Many applications require large computation and high memory bandwidth, such as artificial intelligence applications and HPC applications, and many chip designs provide solutions for these applications. The CPU solves these problems through common low-level methods, so it loses some parallel capabilities and cannot support massive calculations. GPUs provide extreme parallelism for similar computations, such as image creation and processing. However, it is still unable to provide sufficient computing power for some special algorithms in fields such as artificial intelligence applications. Some field-specific ASICs such as TPU focus on customized requirements, providing extremely high computing power and high efficiency. These ASICs are usually ...

AI Technical Summary

Problems solved by technology

These ASICs are usually used as accelerators for some hosts such as CPUs. Because some general operations cannot be completed in these ASICs, there is a lot of data exchange with the host, so it is impossible to achieve high performance and high efficiency for the overall application.

Custom chips are not flexible enough to run new algorithms in the same domain and for applications in other domains

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