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Manufacturing method of multi-fold mask layer

A manufacturing method and mask layer technology, which can be applied to the photolithographic process of the patterned surface, semiconductor/solid-state device manufacturing, and originals for photomechanical processing, etc., can solve the problem of low precision and difficult Further narrow the gap and other issues

Pending Publication Date: 2019-12-17
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a multiple mask layer, which is used to solve the problem of low precision in the manufacture of multiple mask layers in the prior art and the difficulty of further reducing the pitch The problem

Method used

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  • Manufacturing method of multi-fold mask layer
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  • Manufacturing method of multi-fold mask layer

Examples

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Effect test

Embodiment 1

[0113] like Figures 7 to 19 As shown, this embodiment provides a method for fabricating a multiple mask layer, and the fabrication method includes:

[0114] like Figures 7 to 8 As shown, step 1) is first performed, a substrate 201 is provided, a first mask layer 203 is formed on the substrate 201, the first mask layer 203 includes a plurality of imaging mask units 2031, and the imaging mask There is an imaging gap 204 on the substrate 201 between the film units 2031, and the size of the imaging mask unit 2031 depends on the minimum exposure development size capability.

[0115] The substrate 201 includes a layer to be etched, and the layer to be etched may be a semiconductor substrate material, a dielectric material, a metal material, or various stacked materials composed of the above materials.

[0116] The material of the first mask layer 203 includes one selected from the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilic...

Embodiment 2

[0146] like Figure 20 to Figure 33 As shown, this embodiment provides a method for fabricating a multiple mask layer, and the fabrication method includes:

[0147] like Figure 20 ~ Figure 21 As shown, step 1) is first performed, a substrate 201 is provided, a first mask layer 203 is formed on the substrate 201, the first mask layer 203 includes a plurality of imaging mask units 2031, and the imaging mask There are imaging gaps 204 on the substrate 201 between the film units 2031 .

[0148] The substrate 201 includes a layer to be etched, and the layer to be etched may be a semiconductor substrate material, a dielectric material, a metal material, or various stacked materials composed of the above materials.

[0149] The material of the first mask layer 203 includes one selected from the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. In this embodiment, the material of the first mask layer 203 can be selected as photo...

Embodiment 3

[0181] like Figure 34 to Figure 48 As shown, this embodiment provides a method for fabricating a multiple mask layer, and the fabrication method includes:

[0182] like Figure 34 to Figure 35 As shown, step 1) is first performed, a substrate 201 is provided, a bottom mask layer 202 is formed on the substrate 201, a first mask layer 203 is formed on the bottom mask layer 202, and the first mask Layer 203 includes a plurality of imaging mask units 2031 with imaging gaps 204 on the bottom mask layer 202 therebetween.

[0183] The substrate 201 includes a layer to be etched, and the layer to be etched may be a semiconductor substrate material, a dielectric material, a metal material, or various stacked materials composed of the above materials.

[0184] The material of the first mask layer 203 includes one selected from the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. In this embodiment, the material of the first mask la...

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Abstract

The invention provides a manufacturing method of a multi-fold mask layer, which comprises the steps of forming a groove through the stacking configuration of multiple layers of hard masks with different etching selection ratios and self-alignment, exposing the multiple layers of hard masks on the surface by a thinning process, and finally obtaining the multi-fold mask layer through selective etching. According to the manufacturing method of the multi-fold mask layer, a structure similar to an ox horn cannot be formed in the manufacturing process of spacing multiplication, and the accurate etching of the multi-fold mask layer can be greatly improved. According to the invention, the multi-fold mask layer is manufactured by utilizing different stacking configurations and etching speed ratio selection of the multiple mask layers and the method for forming the groove based on self-alignment, the characteristic size of the device can be effectively reduced, and the characteristic density ofthe device is increased. Meanwhile, three times and four times of spacing multiplication can be realized. In addition, the width adjustment of the gap can be realized by controlling the thickness of each mask layer.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, in particular to a method for manufacturing a multiple mask layer. Background technique [0002] With the continuous development of semiconductor technology, integrated circuits become smaller and denser, which provides many advantages for the performance of integrated circuits, but at the same time, due to the limitations of manufacturing equipment, the production of smaller and denser Large integrated circuits are becoming increasingly difficult and expensive to manufacture. Improved processes are therefore used to reduce feature size, thereby increasing the density of integrated circuits. [0003] Pitch doubling or pitch doubling is a method by which the capabilities of lithography can be extended beyond their minimum pitch. An existing method for fabricating a pitch multiplication mask layer includes the following steps: [0004] 1) providing a substrate 101 on which a bottom mas...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/31H01L21/3105H01L21/033G03F1/50
CPCH01L21/31H01L21/31053H01L21/033G03F1/50
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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