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Interstage gain mismatch correction method for pipelined ADC

A mismatch correction and pipeline technology, applied in analog/digital conversion calibration/testing, analog-to-digital converters, electrical components, etc., can solve problems such as large limitations, achieve high real-time performance and improve accuracy

Active Publication Date: 2019-11-26
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

However, this technique requires simultaneous sampling of the same signal, which has too many limitations

Method used

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  • Interstage gain mismatch correction method for pipelined ADC
  • Interstage gain mismatch correction method for pipelined ADC

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Embodiment Construction

[0041] In conjunction with the accompanying drawings, the present invention is further illustrated through the embodiments.

[0042] The gain mismatch in the pipeline ADC will cause non-ideal gaps or steps in the output of the pipeline ADC. Gain mismatch can be corrected by compensating for gaps or steps so that the overall output remains linear. Based on this, if figure 2 As shown, if there is a reference channel and the correction channel to quantize the same input signal at the same time, and the reference channel is ideal, that is, the output is linear, then the inter-stage gain coefficient m can be modified through the digital background 1 , so that the output of the calibration channel maintains the same slope as the reference channel, that is, the same linearity.

[0043] D. out =D 1 +m 1 ·D BE

[0044] Taking the correction of the inter-stage gain mismatch between the i+1-th pipeline and the i-th pipeline of the correction channel in the pipeline ADC as an exam...

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Abstract

The invention discloses an interstage gain mismatch correction method for a pipelined ADC, and belongs to the technical field of analog integrated circuits. Based on the theoretical basis that an ideal ADC input and output characteristic curve is a linear relation, correction signals with opposite injection symbols are used for enabling residual transfer characteristic curves of two channels to beinconsistent, and therefore gain correction of a nonlinear channel is completed through a linear channel. When the pipelined ADC is a split or time-interleaved pipelined ADC, two channels in the split or time-interleaved pipelined ADC can be used as a reference channel and a correction channel respectively; in addition, the same input signal can be quantized twice, one quantization channel is used as a reference channel, the other quantization channel is used as a correction channel, and two virtual channels are realized. According to the invention, the problem of gain mismatch in a pipelinedADC is solved; a mode of solving the slope based on at least three points is provided, and the accuracy is improved compared with a traditional two-point slope method; the method can work in a digital background and has high real-time performance.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and particularly relates to a digital background correction method based on the linear relationship between ADC input and output and using its slope characteristics to complete the gain mismatch between pipeline ADC (Pipeline ADC) stages. Background technique [0002] In the interface circuit between virtual and real world, analog-to-digital converter (ADC) is an indispensable circuit module, and it is particularly important to digitize analog information quickly and accurately. Therefore, high-speed, high-precision ADC has become the key to information processing now. Pipeline ADC (Pipeline ADC) adopts a multi-stage structure to quantize the input signal according to the working method of pipeline. Thanks to this feature, it is the first choice for realizing high-speed and high-precision ADC. [0003] Such as figure 1 Shown is a traditional N-bit Pipeline ADC architecture di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/1028H03M1/1245
Inventor 宁宁罗建李成泽李靖于奇
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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