Convolutional neural network acceleration device based on RISC-V architecture and control method thereof

Abstract

The invention discloses a convolutional neural network acceleration device based on an RISC-V architecture and a control method thereof, and the device comprises a memory used for storing data; a mainprocessor used for sending an expansion instruction; a coprocessor used for receiving the expansion instruction sent by the main processor, reading the input data from the memory according to the received expansion instruction, performing grouping operation processing on the input data to obtain output data, and storing the output data into the memory; the main processor is also used for readingthe output data stored by the coprocessor from the memory; wherein the operation processing comprises convolution operation, activation operation and pooling operation. According to the invention, thecoprocessor executes the time-consuming operation based on the expansion instruction, can adapt to input data of different sizes, flexibly performs combined operation on convolution, pooling and activation operations of the convolutional neural network, and can adapt to various lightweight convolutional neural networks. The method can be widely applied to the technical field of processors.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a convolutional neural network acceleration device based on RISC-V architecture and a control method thereof. Background technique [0002] Glossary: [0003] GPU: Graphics Processing Unit, also known as display core, visual processor, and display chip, is a microprocessor that specializes in image computing on personal computers, workstations, game consoles, and some mobile devices. [0004] FPGA: Field-Programmable Gate Array, that is, Field Programmable Gate Array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It appeared as a semi-custom circuit in the field of application-specific integrated circuits, which not only solved the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of original programmable device gates. [0005] ASIC: Application Specific Integrated Circuit, that is...

AI Technical Summary

Problems solved by technology

In the current mainstream computing platforms, GPU power consumption and cost are too high, FPGA resources and speed are limited, and ASIC has poor versatility

In order to meet the calculation requirements of some cost-sensitive fields such as the Internet of Things or flexible algorithms and complex steps, it is more common to use a CPU platform, but the current general-purpose CPU is difficult to meet the large-scale calculation of neural networks.

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