Semiconductor device and electronic device

Abstract

The invention provides a semiconductor device and an electronic device. The semiconductor device comprises a semiconductor substrate, a first redistribution dielectric layer and a second redistribution dielectric layer, wherein the semiconductor substrate comprises a main chip region, an interconnection layer is formed on the semiconductor substrate in the main chip region, and a sealing ring is formed between the main chip region and a cutting channel; the first redistribution dielectric layer is formed on the interconnection layer and the second redistribution dielectric layer is formed on the first redistribution layer; a redistribution layer electrically connected with the interconnection layer is formed in the first redistribution dielectric layer; the edge of the first redistributiondielectric layer is located above the sealing ring; and the edge of the second redistribution dielectric layer is located above the first redistribution dielectric layer. According to the semiconductor device provided in the invention, the edge stress of the redistribution dielectric layer can be reduced, the risk of cracking is reduced, and the chip can be prevented from being damaged.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device and an electronic device. Background technique [0002] In the process of integrated circuit design and manufacturing, packaging is an indispensable and important part, and it is also the final stage of semiconductor integrated circuit manufacturing. With the increasingly powerful functions of integrated circuits, higher and higher performance and integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, which puts forward higher and higher requirements for the packaging of integrated circuits. [0003] During chip packaging, it is necessary to connect the pads on the top layer of the ch...

AI Technical Summary

Problems solved by technology

During packaging, the redistribution dielectric layer shrinks at high temperature, which creates a certain stress on the passivation layer below, causing cracks in the passivation layer, and the cracks easily extend to the functional area of ​​the chip, resulting in chip failure

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