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A widely distributed low-jitter synchronous clock distribution system and method

A technology for synchronizing clocks and distribution systems, applied in automatic power control, electrical components, etc., can solve problems such as large time jitter of optical modules and impact on system stability, and achieve an efficient and concise solution

Active Publication Date: 2022-04-19
LASER FUSION RES CENT CHINA ACAD OF ENG PHYSICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, in the prior art, direct optical transmission is commonly used for the clock distribution system in a wide space, mainly by converting the clock signal into an optical signal, and then converting and recovering the clock signal, so that if the required clock frequency is low , the time jitter introduced by the optical module is relatively large, which has a great impact on the stability of the system

Method used

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  • A widely distributed low-jitter synchronous clock distribution system and method
  • A widely distributed low-jitter synchronous clock distribution system and method

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Embodiment 1

[0045] Embodiment 1 of the present invention provides a widely distributed low-jitter synchronous clock distribution system. The system is mainly composed of a precise timing generation component and a phase-locked clock generator. The precision timing generating component generates a high-frequency clock optical data stream and a low-frequency clock and reset code mixed-encoded optical data stream. The phase-locked clock generator recovers the low-frequency clock and the reset start signal through the clock and data recovery module. The reset code is extracted from the recovered data under the action of the recovered clock, and a reset pulse signal is generated under the action of the recovered clock. The micro-step delay module provides a cycle center reset pulse signal by performing a micro-step delay on the reset pulse signal. The phase-locked clock generator uses clock recovery technology to recover a low-jitter high-frequency clock signal from the high-frequency clock op...

Embodiment 2

[0056] This embodiment provides a method for providing widely distributed low-jitter synchronous clock distribution, and the method is implemented based on any of the aforementioned widely distributed low-jitter synchronous clock distribution systems. The method comprises the steps of:

[0057] Step S1, initialization, generating and outputting a reference clock by an external reference clock source 11;

[0058] Step S2, process and convert the reference clock output by the external reference clock source 11, so as to simultaneously generate low-frequency clock and high-frequency clock, and transmit them in the form of two optical data streams;

[0059] Further, step S2 specifically includes:

[0060] Step S2.1, the reference clock output by the external reference clock source 11 is a low-frequency clock signal, and the low-frequency clock signal is simultaneously provided as an input to the clock and reset signal encoding module 12 and the phase-locked frequency multiplier 1...

Embodiment 3

[0076] It is necessary to perform a micro-step delay on the reset pulse signal generated by the micro-step delay module 19 in the foregoing embodiment, move the reset pulse signal to the center of the clock cycle, and output a low-jitter reset solution. In the frequency divider, the frequency division state of the frequency divider is in an uncertain state when it is turned on, which will cause the output of the frequency divider to be in an uncertain state, and the jitter is large. In order to ensure the low jitter output of the frequency It is necessary to reset the frequency divider once every time, and fix the output state of the frequency divider. The frequency divider operates at the edge of the high-frequency clock, and when the reset signal is at the edge of the high-frequency clock, the clock frequency division output will be in an indeterminate state, that is, the output clock has periodic jitter. The position of the reset signal can be adjusted by the micro-step del...

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Abstract

The invention discloses a widely distributed low-jitter synchronous clock distribution system and method, belonging to the technical field of synchronous control. The system includes a precise timing generation component 1 and a first phase-locked clock generator 2, the precise timing generation component 1 is used to generate high-frequency and low-frequency clock signals, and provide the first phase-locked clock in the form of an optical data stream Generator 2, the first phase-locked clock generator 2 is used to obtain a corresponding target frequency clock signal. The present invention uses a phase-locked frequency multiplication module to multiply the frequency of the clock to be distributed to a higher frequency, and the distribution and clock recovery technology after the phase-locked frequency multiplication of the distribution clock ensures the low jitter characteristics of the distribution clock; The method of improving the re-division reduction and uniformly resetting the frequency divider can obtain a clock signal with low time jitter and synchronous alignment characteristics. The scheme is efficient and simple, and can be widely used in various solid-state laser devices, medical equipment, high-speed circuit testing, etc. Research tests.

Description

technical field [0001] The invention belongs to the technical field of synchronous control, and specifically relates to a wide-distributed low-jitter synchronous clock distribution system and method, which can be applied to research and testing of various solid-state laser devices, medical equipment, and high-speed circuit testing. Background technique [0002] Clock distribution is widely used in computers, communications, and consumer electronics products, and is mainly used for synchronization and latching of system sending and receiving data. If the jitter of the clock signal reaches the receiver, it may have a serious impact on the data reception and system stability, so the measurement, analysis and processing of the clock jitter is very important. At present, in the prior art, direct optical transmission is commonly used for the clock distribution system in a wide space, mainly by converting the clock signal into an optical signal, and then converting and recovering t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/18H03L7/10
CPCH03L7/18H03L7/10
Inventor 王深圳王超党钊陈骥张雄军陈文棋李克洪郑奎兴彭志涛陈德怀沈昊苏东赖贵友唐海波
Owner LASER FUSION RES CENT CHINA ACAD OF ENG PHYSICS
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