SRAM type FPGA double-port RAM single event upset prevention reinforcing device for spacecraft

Abstract

The invention relates to an SRAM type FPGA double-port RAM single event upset prevention reinforcing device for a spacecraft, and belongs to the technical field of aerospace electronics. The single event upset prevention reinforcing device comprises a double-port RAM module and an arbitration refresher. The double-port RAM module comprises two sets of completely independent ports which are a firstport and a second port respectively, and each port comprises a data line, an address line, a read enable control line and a write enable control line. The user data is written into and read out of the double-port RAM module through the first port. The arbitration refresher reads the user data stored in the double-port RAM module through the second port and then writes the user data into the double-port RAM again under the condition that the user access data is not influenced, so that the double-port RAM is refreshed. According to the device, the problem of single event upset prevention reinforcement of the BlockRAM in the spacecraft SRAM type FPGA is solved.

Description

technical field [0001] The invention belongs to the technical field of aerospace electronics, and relates to an anti-single-event flipping reinforcing device using SRAM-type FPGA dual-port RAM for spacecraft. Background technique [0002] SRAM-type FPGAs are widely used in the design of spacecraft electronic systems. At present, the anti-radiation hardening of traditional SRAM FPGA adopts the three-mode redundancy plus scrubbing mechanism to improve reliability. For example: [0003] In the article "SRAM Type FPGA Anti-Single Event Flipping Design for Aerospace" (Spacecraft Environmental Engineering, Vol. Part of the anti-single event flipping design scheme adopts general-purpose self-correcting macros. This solution is achieved through internal BlockRAM triple-mode redundancy. [0004] Patent CN201610939803.2 is named as a RAM data reliability reinforcement device and method based on SRAM FPGA, which describes the use of Hsiao codes as error correction codes to realize ...

AI Technical Summary

Problems solved by technology

[0006] First of all, the overhead of three-mode redundancy for the FPGA internal BlockRAM is huge, it takes up a lot of additional storage resources, and the real-time processing is not strong; moreover, the long-term flip accumulation also increases the possibility of data errors caused by the flipping of two of the three modes;

[0007] Secondly, the refresh mechanism only refreshes the resources inside the FPGA except BlockRAM and RAM interconnection, and cannot cover BlockRAM

Therefore, when a single event flip occurs in the long-term in-orbit RAM area data, the refresh mechanism cannot be corrected

[0008] Therefore, there is still a lack of effective anti-single event flipping means for BlockRAM for long-term important data storage

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