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Hash join operator acceleration method and system based on FPGA-DDR

An operator and connection key technology, applied in the field of hash connection operator acceleration methods and systems, can solve the problem that the scale and quantity of high-speed Block-RAM cannot meet the requirements of the number of large databases, so as to compensate for bandwidth problems, accelerate effects, and improve The effect of operating efficiency

Active Publication Date: 2019-07-05
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For some small-scale and high-real-time requirements, it is possible to directly access and operate in the high-speed Block-RAM inside the FPGA. Number of databases required

Method used

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  • Hash join operator acceleration method and system based on FPGA-DDR
  • Hash join operator acceleration method and system based on FPGA-DDR
  • Hash join operator acceleration method and system based on FPGA-DDR

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Experimental program
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Effect test

Embodiment 1

[0052] A kind of FPGA-DDR-based hash connection operator acceleration method of the present invention, DDR memory is an external memory, stores tuple, hash table and linked list through DDR memory; FPGA chip is configured with on-chip register, tuple request module, Hash calculation module, write link list module, hash table processing module, update link list module, detection link list module, judgment module, analysis module, connection tuple data / pointer module, FIFO module, synchronous FIFO module and loop FIFO module , wherein the on-chip register resources include the base address of the database, the base address of the database tuple, the base address of the hash table, the base address of the linked list, and the base addresses of the above-mentioned modules; under the cooperation of the above-mentioned DDR memory and the FPGA chip, through The construction phase and detection phase of the hash connection execute parallel multi-thread operations to realize the constru...

Embodiment 2

[0085] The hash connection operator acceleration system based on FPGA-DDR of the present invention includes a DDR memory and an FPGA chip, and the DDR memory is used to store tuples, hash tables and linked lists, and the tuples include constructing tuples and detecting tuples, and hashing The table stores the head node of each linked list, and the connection keys with the same hash value belong to the same hash bucket, and the elements in each hash bucket are linked through a linked list;

[0086] The FPGA chip is configured with the following modules:

[0087] A tuple request module that builds a thread for each tuple and generates a request for its join key;

[0088] Hash calculation module, used to calculate the hash value of the connection key;

[0089] Write the linked list module, which is used to write the connection key key value and tuple pointer into the new node of the corresponding hash bucket linked list;

[0090] The hash table processing module is used to gene...

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Abstract

The invention discloses a Hash join operator acceleration method and system based on an FPGA-DDR, and belongs to the field of acceleration of a memory database. The technical problem to be solved is how to realize acceleration operation in a construction stage and a detection stage of a Hash connection algorithm. The method comprises: storing a tuple, a hash table and a linked list through a DDR memory, hash calculation is conducted through an FPGA chip, the hash table and the linked list are updated, and the FPGA chip is controlled to conduct interactive communication facing the DDR memory; under the cooperation of the DDR memory and the FPGA chip, parallel multi-thread operation is executed in the construction stage and the detection stage of the hash connection to realize the construction and matching of the hash table. The system comprises a DDR memory and an FPGA chip, the DDR memory is used for storing a tuple, a hash table and a linked list, and the FPGA chip is used for storinga base address, executing hash calculation, updating the hash table and the linked list and controlling the DDR memory to perform interactive communication.

Description

technical field [0001] The invention relates to the field of memory database acceleration, in particular to an FPGA-DDR-based hash join operator acceleration method and system. Background technique [0002] As the amount of information continues to increase, the scale of the database is getting larger and larger, and the real-time requirements of data analysis tasks are becoming more and more stringent. For some small-scale and high-real-time requirements, it is possible to directly access and operate in the high-speed Block-RAM inside the FPGA. The number of databases required. Therefore, in many application scenarios, people still need to access FPGA external memory storage (DDR3 / DDR4) to build a larger-scale memory database. In-memory databases based on DDR memory have larger data capacity than on-chip solutions based on Block-RAM, and have lower response delays than traditional disk database solutions. It has more research and practical application value. [0003] Ba...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/22G06F16/2453G06F5/06
CPCG06F5/065Y02D10/00
Inventor 齐乐李凯一彭福来吴登勇
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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