A universal convolutional neural network accelerator based on a one-dimensional pulsation array

Abstract

The invention discloses a universal convolutional neural network accelerator based on a one-dimensional pulsation array. An AXI4 bus interface is used for realizing loading of a mode configuration instruction, reading of to-be-calculated data and batch sending of result data. The mode configurator configures each functional module as a corresponding working type through the mode configuration instruction; The data scheduling module can concurrently perform tasks of caching data to be calculated, reading calculation data, caching convolution results, processing the convolution results and outputting the convolution results; The convolution calculation module adopts a one-dimensional pulsation array mode to carry out convolution calculation; The to-be-calculated data cache region, the convolution result cache region and the output result buffer FIFO are used for caching corresponding data; And the result processing module carries out common result processing operation in the convolutional neural network. The accelerator can be compatible with different calculation types in a convolutional neural network, high-parallelism calculation is carried out to effectively accelerate, and onlya lower off-chip memory access bandwidth requirement and a small amount of on-chip memory resources are needed.

Description

Technical field [0001] The invention belongs to the technical field of electronic information and deep learning, and in particular relates to a general convolutional neural network hardware accelerator based on a one-dimensional systolic array (1-DSystolic Array). Background technique [0002] In recent years, deep convolutional neural networks have received extensive attention recently. From the Google Brain team’s use of deep neural networks to "recognize cats" in 2012 to the invincibility of AlphaGO / AlphaZero of the Deepmind team on the Go field in 2016 / 17, convolution "Deep learning" represented by neural networks has attracted not only the attention of the public, but also great interest from academia and industry. Through the efforts of researchers and engineers, convolutional neural networks have been widely used in many directions, such as image recognition, target detection, and natural language processing. [0003] However, high-performance convolutional neural networks ...

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Problems solved by technology

[0003] However, the amount of parameters and calculations required for high-performance convolutional neural networks is also very large. For example, for tasks such as detection / recognition / semantic segmentation of high-definition images, the weight data of the model alone is as high as hundreds of megabytes, even for the inference process. It also often requires tens to hundreds of billions of multiplication and accumulation operations. The data access frequency, calculation amount, and storage space requirements all bring great pressure to the computing platform. It is necessary to find a way to build a high-performance general-purpose convolutional neural network. hardware accelerator to solve the above problems, the case arises from this

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