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A method for operating three-dimensional flash memory array cells with variable programming levels

A technology of unit operation and flash memory array, which is applied in the field of three-dimensional flash memory array unit operation, and can solve problems such as the description of multi-valued storage implementation methods

Active Publication Date: 2021-08-03
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The three-dimensional vertical NAND storage string was first disclosed in 2001, however, each cell of this NAND storage string can only store one bit of data
However, the patent does not describe the implementation method of multi-value storage

Method used

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  • A method for operating three-dimensional flash memory array cells with variable programming levels
  • A method for operating three-dimensional flash memory array cells with variable programming levels
  • A method for operating three-dimensional flash memory array cells with variable programming levels

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Embodiment Construction

[0028] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0029] Such as figure 1 As shown, when performing an erase operation, the microprocessor controls the erase control unit to send an erase command, and controls the address information to be written into the address decoder, controls the drive voltage generator to generate a voltage drive signal (erase voltage), and finally passes the read The write circuit performs an erase operation on the selected block structure. After the erase operation of the selected block structure is completed, the detection control unit and the count control unit sequentially gate and verify the states of different flash...

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Abstract

The invention discloses a method for operating a three-dimensional flash memory array unit with a variable programming level, comprising: S1. receiving an erasing operation instruction and address information; S2. performing an erasing operation on a selected block structure; S3. receiving multi-level programming Instruction and address information; S4. Judging whether the address overflows, if so, enter S5, otherwise, receive the programming level information of the target unit, and enter S6; S5. The programming operation of the selected block structure is completed and ends; S6. According to the multi-level programming Instructions, address information, and the programming level information of the target cell are used to perform multi-level programming operations on the current flash memory cell; S7. judge whether the difference between the threshold voltages is not less than the preset minimum interval voltage, if so, change the address information, enter S3, and perform programming operation of the next flash memory unit; otherwise, re-perform multi-level programming operations on the current flash memory unit no more than a predetermined number of times. The invention programs the target number of stages of the flash memory unit, so that the threshold voltage is accurate to a predetermined value, thereby precisely controlling its data state.

Description

technical field [0001] The invention belongs to the technical field of semiconductor storage, and more specifically relates to a method for operating a three-dimensional flash memory array unit with variable programming levels. Background technique [0002] Flash memory (Flash), as a non-volatile memory, can be divided into NAND flash memory and NOR flash memory. Each memory cell of NOR flash memory is independently connected to the bit line and word line, so it has good random storage characteristics, and multiple memory cells of NAND flash memory are connected in series, so it has good integration characteristics and is often used in high-density flash memory arrays realization. As the feature size decreases, the flash memory array with planar structure will face problems such as increased crosstalk between adjacent cells and too few electrons stored in the floating gate. In order to continue to increase storage density, three-dimensional vertically stacked flash memory ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10G11C16/34G11C16/14
Inventor 缪向水闫鹏童浩
Owner HUAZHONG UNIV OF SCI & TECH
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