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Trench IGBT chip

A technology of grooves and chips, applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of unfavorable and impacted chip turn-on and turn-off, optimize the chip conduction voltage drop, avoid mutual interference, and reduce input and output The effect of capacitance

Active Publication Date: 2019-05-14
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existence of a large number of accompanying regions (accompanied gates and accompanying wells) causes the parasitic capacitance of the chip to have an adverse effect on the turn-on and turn-off of the chip.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] figure 1 It is a schematic structural diagram of a trench IGBT chip according to Embodiment 1 of the present invention. Such as figure 1 As shown, it may include an N-type substrate 1, a plurality of strip-shaped trench gates 2, a plurality of auxiliary gates 3, a strip-shaped accompanying gate 4, an N+ region 5, a P+ region 61, a P well region 7, and an N well Region 8, oxide layer 9, emitter metal layer 10, N-type buffer layer 11, anode P region 12 and anode metal layer 13.

[0041] A plurality of strip-shaped trench gates 2 are respectively located in a plurality of trenches etched downward from the upper surface of the N-type substrate 1 , and extend along the surface of the N-type substrate 1 and are distributed in parallel.

[0042] A plurality of auxiliary gates 3 are respectively located in a plurality of trenches formed by etching the upper surface of the N-type substrate 1 downwards, and are perpendicular to the length direction of the strip-shaped trench ga...

Embodiment 2

[0054] Figure 6 It is a schematic structural diagram of a trench IGBT chip according to Embodiment 2 of the present invention. Such as Figure 6 As shown, it may include an N-type substrate 1, a plurality of strip-shaped trench gates 2, a plurality of auxiliary gates 3, an N+ region 5, a P+ region 61, a P well region 7, an N well region 8, an oxide layer 9, Emitter metal layer 10 , N-type buffer layer 11 , anode P region 12 and anode metal layer 13 .

[0055] A plurality of strip-shaped trench gates 2 are respectively located in a plurality of trenches etched downward from the upper surface of the N-type substrate 1 , and extend along the surface of the N-type substrate 1 and are distributed in parallel.

[0056] A plurality of auxiliary gates 3 are respectively located in a plurality of trenches formed by etching the upper surface of the N-type substrate 1 downwards, and are perpendicular to the length direction of the strip-shaped trench gate 2, so that the plurality of s...

Embodiment 3

[0066] Figure 7 It is a schematic structural diagram of a trench IGBT chip according to Embodiment 3 of the present invention. Such as Figure 7 As shown, it may include an N-type substrate 1, a plurality of strip-shaped trench gates 2, a plurality of auxiliary gates 3, a strip-shaped accompanying gate 4, an N+ region 5, a P+ region 62, a P well region 7, and an N well region. Region 8, oxide layer 9, emitter metal layer 10, N-type buffer layer 11, anode P region 12 and anode metal layer 13.

[0067] A plurality of strip-shaped trench gates 2 are respectively located in a plurality of trenches etched downward from the upper surface of the N-type substrate 1 , and extend along the surface of the N-type substrate 1 and are distributed in parallel.

[0068] A plurality of auxiliary gates 3 are respectively located in a plurality of trenches formed by etching the upper surface of the N-type substrate 1 downwards, and are perpendicular to the length direction of the strip-shaped...

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Abstract

The invention discloses a trench IGBT chip comprising the following parts: an N-type substrate; a plurality of strip trench gates extending along the surface of the N-type substrate and arranged in parallel; a plurality of auxiliary gates perpendicular to the length direction of the strip trench gates to isolate the region between the plurality of strip trench gates into a plurality of active regions and a plurality of accompanying regions, wherein the active regions and the accompanying regions are alternately arranged, the active regions are provided with an N+ region, a P+ region, a P wellregion and an N well region, and the accompanying regions are provided with an N+ region, a P+ region, a P well region and an N well region; and an emitter metal layer in contact with the N+ region and the P+ region. The invention can effectively isolate the active regions and the accompanying regions by introducing auxiliary gates between the active regions and the accompanying regions in the trench IGBT chip unit to avoid mutual interference between the two during working, thereby separately designing the active regions and the accompanying regions to achieve overall optimization of chip performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a trench IGBT chip. Background technique [0002] Insulated gate bipolar transistor (IGBT) is a power semiconductor device that combines MOSFET and bipolar transistor (BJT). Due to its high current density and other characteristics, it is widely used in rail transit, smart grid, electric vehicles, new energy development and other fields. [0003] With the mature application of trench technology in the IGBT device structure, the current channel has been successfully transformed from the surface horizontal to the vertical in the body, effectively eliminating the JFET effect in the planar gate body, and at the same time reducing the cell size, making the channel density no longer Limited by the surface area of ​​the chip, the cell density is greatly increased, thereby greatly increasing the current density of the chip. However, with the increase of the trench gate de...

Claims

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Application Information

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IPC IPC(8): H01L29/423H01L29/739
Inventor 朱春林王亚飞王彦刚覃荣震戴小平罗海辉刘国友
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD
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