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A cache partition division method for a reconfigurable system

A cache partition and system reconstruction technology, applied in general-purpose stored program computers, architectures with a single central processor, etc., can solve performance changes, affect throughput, reduce cache utilization, etc., to reduce bandwidth requirements and performance. Optimized, fine-tuned effects

Active Publication Date: 2019-05-03
XI AN JIAOTONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This causes large performance variations, hampers Quality of Service (QoS) guarantees, and can reduce cache utilization, impacting overall throughput

Method used

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  • A cache partition division method for a reconfigurable system
  • A cache partition division method for a reconfigurable system
  • A cache partition division method for a reconfigurable system

Examples

Experimental program
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Embodiment Construction

[0053] main feature:

[0054] 1. Utilization-based partitioning method (Utility-BasedCache Partitioning) and invalid scaling (Futility Scaling), reasonably divide the cache area.

[0055] 2. Introduce two new data - the amount of data overlap and the number of iterations, and the data can be tracked and calculated through the hardware.

[0056] The main advantage

[0057] 1. Combining the advantages of Utility-Based Cache Partitioning and Utility Scaling, the cache area is divided reasonably, and the appropriate content in the main memory is placed in the appropriate cache partition to improve system performance.

[0058] 2. Correct the original cache division by using data overlap and iteration times to obtain a more reasonable scaling factor α and invalidity f, and accurately and meticulously control the partition size, so that partitions with high performance will allocate more cache resources, optimize performance.

[0059] The cache division method proposed by the presen...

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PUM

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Abstract

The invention discloses a cache partition division method of a reconfigurable system, which comprises the following steps of: 1) when a plurality of coarse-grained reconfigurable arrays CGRA process data, managing shared on-chip caches by adopting invalid zooming FS (Free Scale Analysis) so as to reduce the bandwidth requirement of an off-chip memory; and 2) introducing new data-data overlap amount and iteration times for correction on the basis of invalid scaling FS during cache partitioning, so as to achieve performance optimization. The invention is oriented to a reconfigurable processor. Statistics of the overlap amount and the number of iterations of the data are newly added into an original partitioning method, the data are corrected and improved, the adverse effects of overlap of the data and calculation imbalance among the CGRAs in a plurality of CGRA platforms are avoided to a certain degree, and the cache performance in a reconfigurable processor is improved.

Description

technical field [0001] The invention belongs to the field of high-speed cache partitions, and in particular relates to a cache partition partition method for a reconfigurable system. Background technique [0002] General-purpose computers and ASICs represent two extremes of computing, with general-purpose computers having the greatest flexibility and low performance, and ASICs having the highest performance and the least flexibility. But now there are many application requirements that require both high performance and certain flexibility. For example, a multimedia application may include subtasks such as data parallel processing, bit processing, irregular calculation, high-precision word operations, and operations with real-time requirements. The processing system is required to be able to flexibly handle the above subtasks and achieve certain performance. Many other applications have similar requirements, such as data encryption, artificial intelligence, etc., and these a...

Claims

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Application Information

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IPC IPC(8): G06F15/78
Inventor 杨晨刘童博王逸洲侯佳耿莉
Owner XI AN JIAOTONG UNIV
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