Method for forming channel hole of three-dimensional memory
A memory and channel technology, used in semiconductor devices, electrical solid-state devices, electrical components, etc., can solve the problems of too large CD of deep-hole channel holes, reduced distance between holes and too large top key size, etc. , to achieve the effect of good top width, reduced pattern size, and reduced etching difficulty
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[0018] The specific implementation of the method for forming the channel hole of the three-dimensional memory provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0019] Please refer to Figure 1 to Figure 7 It is a structural schematic diagram of the formation process of the channel hole of the three-dimensional memory according to a specific embodiment of the present invention.
[0020] Please refer to figure 1 1. A substrate 100 is provided, the surface of the substrate 100 has a stacked structure; a mask layer 130 is formed on the stacked structure.
[0021] The substrate 100 can be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, etc.; according to the actual requirements of the device, a suitable semiconductor material can be selected as the substrate 100, which is not limited here. In this specific implementation manner, the substrate 100 is a single crystal silicon wafer. ...
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