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Method for forming channel hole of three-dimensional memory

A memory and channel technology, used in semiconductor devices, electrical solid-state devices, electrical components, etc., can solve the problems of too large CD of deep-hole channel holes, reduced distance between holes and too large top key size, etc. , to achieve the effect of good top width, reduced pattern size, and reduced etching difficulty

Active Publication Date: 2021-08-31
YANGTZE MEMORY TECH CO LTD
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  • Claims
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AI Technical Summary

Problems solved by technology

The formation of the channel hole with high aspect ratio requires an effective hard mask as a sacrificial layer. The hard mask commonly used in the prior art is mainly an amorphous carbon layer (ACL). When the thickness of the ACL is not enough, it will The top key dimension (CD) after channel hole etching is too large, resulting in a reduced hole-to-hole distance
To solve the above problems by thickening the ACL, it is necessary to correspondingly increase the thickness of the oxygen-doped silicon nitride, anti-reflection coating and photoresist on the surface of the ACL layer to improve the lithography effect. difficult to achieve
[0004] Therefore, under the current process conditions, the problem of excessive CD at the top of the deep channel hole cannot be effectively solved.

Method used

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  • Method for forming channel hole of three-dimensional memory

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Embodiment Construction

[0018] The specific implementation of the method for forming the channel hole of the three-dimensional memory provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Please refer to Figure 1 to Figure 7 It is a structural schematic diagram of the formation process of the channel hole of the three-dimensional memory according to a specific embodiment of the present invention.

[0020] Please refer to figure 1 1. A substrate 100 is provided, the surface of the substrate 100 has a stacked structure; a mask layer 130 is formed on the stacked structure.

[0021] The substrate 100 can be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, etc.; according to the actual requirements of the device, a suitable semiconductor material can be selected as the substrate 100, which is not limited here. In this specific implementation manner, the substrate 100 is a single crystal silicon wafer. ...

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Abstract

The invention relates to a method for forming a channel hole of a three-dimensional memory, comprising: providing a substrate, a stack structure is formed on the surface of the substrate; forming a mask layer on the stack structure; etching the mask layer to On the surface of the stack structure, a first pattern with a first critical dimension is formed in the mask layer; a protective layer covering at least the sidewall surface of the etched pattern is formed, so that the size of the first pattern is reduced, forming a pattern with The second pattern of the second critical dimension: using the mask layer and the protective layer as a mask, etching the stacked structure to the substrate to form a channel hole. The above method can effectively control the size of the channel hole and reduce the difficulty of forming the channel hole.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a channel hole of a three-dimensional memory. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] During the formation process of the three-dimensional memory, multiple layers of insulating layers and sacrificial layers stacked alternately are first formed on the surface of the substrate, and then the insulating layers and sacrificial layers are etched to form ch...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582H10B41/35H10B41/27H10B43/27H10B43/35
CPCH10B41/35H10B41/27H10B43/35H10B43/27
Inventor 李飞向银松王猛任连娟
Owner YANGTZE MEMORY TECH CO LTD
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