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Power-to-ground ESD protection unit and double-power broadband linear voltage stabilizer protection structure

A technology of ESD protection and power supply, applied in the direction of instruments, regulating electrical variables, control/regulating systems, etc., can solve the problems of increasing the difficulty of anti-static protection structure design and complicating the design of anti-static network, so as to improve the electrostatic discharge capability. Effect

Active Publication Date: 2019-02-22
XIAN MICROELECTRONICS TECH INST
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  • Summary
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this linear regulator structure, in order to achieve low dropout and broadband performance, dual power supplies are used, and the adjustment port (Adj) appears on the external pins, so the design of the dual power supply anti-static protection structure against ground is more difficult, and the dual power supply circuit Complicated antistatic network design between ports of the overall chip

Method used

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  • Power-to-ground ESD protection unit and double-power broadband linear voltage stabilizer protection structure
  • Power-to-ground ESD protection unit and double-power broadband linear voltage stabilizer protection structure
  • Power-to-ground ESD protection unit and double-power broadband linear voltage stabilizer protection structure

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Embodiment 1

[0033] Based on standard bipolar process technology, the input voltage V in the full chip IN1 The range is 3.3V ~ 7V, the input voltage V IN2 The range is 1.4V ~ 7V, using such as image 3 shown in the full-chip ESD protection network, V IN1 , V IN2 , Adj, V OUT There is a reverse diode structure to the ground, so the ports of the chip can be isolated from each other.

[0034] When V IN1 When an ESD event occurs between the port and the ground port, if V IN1 port is high voltage, Q n1 , Q n2 After the reverse breakdown of the transistor BE junction, the transistor Q in the Darlington transistor n3 and Q n4 turns on, the ESD current flows through the transistor Q in the Darlington n3 and Q n4 Bleed to the bottom; if V IN1 port is low voltage, the ESD current is driven by the diode D 1 Bleed to V IN1 Port; V IN2 ESD event between port and ground port and V IN1 The port situation is the same and will not be repeated.

[0035] When an ESD event occurs between the ...

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Abstract

The invention discloses a power-to-ground ESD protection unit and a double-power broadband linear voltage stabilizer protection structure. The characteristics of a bipolar transistor BE junction, RC delay and Darlington NPN transistor are utilized to construct a power-to-ground electrostatic protection unit, and the characteristics of the electrostatic protection unit and bipolar transistor BE areutilized to construct a double-power broadband bipolar linear voltage stabilizer full-chip electrostatic protection network. In the normal state of a chip, it is ensured that IO ports are isolated from one another, a full-chip electrostatic leakage access is constructed to the maximum extent, the full-chip antistatic capacity of a double-power bipolar linear voltage stabilizer is improved, and the antistatic protection network can be popularized to other double poles and analog circuits of a BCD technology.

Description

technical field [0001] The invention belongs to the technical field of bipolar analog integrated circuits, and in particular relates to a power supply-to-ground ESD protection unit and a dual power supply broadband linear voltage regulator protection structure. Background technique [0002] Linear regulators are an important part of today's electronic systems, and are developing towards high power density, high conversion efficiency, high integration, low voltage output, and fast load transient response. The output adjustment transistor of the linear regulator adopts PNP transistor or PMOS transistor to realize the function of low dropout voltage, but due to the large output impedance of the circuit, the load transient response is slow; if the output adjustment transistor adopts NPN transistor or NMOS transistor, it realizes Faster load transient response, but its input and output pressure difference is large; if the linear regulator is powered by dual power supplies, the co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/569
CPCG05F1/569
Inventor 季轻舟
Owner XIAN MICROELECTRONICS TECH INST
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