Downlink level shifting circuit with low operating voltage

Abstract

A downlink level shifting circuit includes a high side input network, a common gate voltage-withstanding structure and a low side latch circuit; the high side input network consists of two parallel PMOS devices of a common source structure, and transmits an input signal to the common gate voltage-withstanding structure; the common gate voltage-withstanding circuit includes a pair of common gate PMOS transistors, a pair of common gate NMOS transistors and two clamp diodes; and the low side latch circuit includes two pairs of NMOS transistors used as linear resistors and a latch structure formedby a pair of cross-coupled NMOS devices, and enables a high-side signal to be transmitted to a low-voltage region when a high-side voltage difference is very small.

Description

technical field [0001] The present invention relates to a level shift circuit in the field of half-bridge drive technology, in particular to a low working voltage downlink level shift circuit that converts a high-voltage level signal into a low-voltage level signal Background technique [0002] With the rapid development of electronic power technology, especially the increasingly wide application of high-frequency self-turn-off components such as IGBT and MOSFET, the design of the drive circuit is very important, especially the high-voltage integrated circuit HVIC drive. A good driving circuit can ensure the high-performance operation of the HVIC chip, such as excellent system reliability and efficiency. In current consumer and industrial applications, HVICs are widely used in many fields, such as variable frequency motor drives, switching power supplies, and electronic ballasts. [0003] figure 1 is the internal block diagram of a traditional HVIC drive circuit. A tradit...

AI Technical Summary

Problems solved by technology

Correspondingly, although this structure solves the withstand voltage problem between the high-side and low-side levels, when the voltage between the high-side high-level VB and the high-side low-level VS in the high-voltage region is low, it will make the NMOS transistor MN3 1. The gate voltage of MN4 is low, and MN3 and MN4 cannot work normally, resulting in the failure of the entire circuit to work normally.

Images