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MOSFET (metal oxide semiconductor field effect transistor) with semi-insulating region and preparation method thereof

A semi-insulating and insulating gate layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of low avalanche breakdown resistance of MOSFET, reduce leakage current, improve UIS robustness, improve Avalanche resistance effect

Active Publication Date: 2018-08-17
ANHUI UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] Aiming at the problem of low avalanche breakdown tolerance of MOSFET in the prior art, the present invention provides a MOSFET containing a semi-insulating region and a preparation method thereof

Method used

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  • MOSFET (metal oxide semiconductor field effect transistor) with semi-insulating region and preparation method thereof
  • MOSFET (metal oxide semiconductor field effect transistor) with semi-insulating region and preparation method thereof
  • MOSFET (metal oxide semiconductor field effect transistor) with semi-insulating region and preparation method thereof

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Effect test

Embodiment 1

[0046] The MOSFET containing the semi-insulating region of this embodiment, such as figure 2 As shown, the semi-insulating region 222 is located below the base region 22 doped with the semiconductor of the first conductivity type and the source region 21 doped with the semiconductor of the second conductivity type arranged side by side. Type semiconductor doped drift layer 12 contacts.

[0047] By setting the semi-insulating region 222, the area where the MOSFET parasitic BJT exists is greatly reduced, thereby greatly reducing the number of parasitic BJT, only a small amount of parasitic BJT still exists in the shallow base area, but due to the great reduction in the number of parasitic BJT , thereby reducing the current in the MOSFET under UIS conditions, limiting the temperature rise, and increasing the avalanche breakdown time of the MOSFET from the theoretical 8 microseconds to 38 microseconds, increasing the time integral of the voltage to the current, and improving the ...

Embodiment 2

[0052] The MOSFET containing the semi-insulating region of this embodiment, such as figure 2 As shown, a further improvement is made on the basis of Embodiment 1. The width of the semi-insulating region 222 is equal to the sum of the widths of the base region 22 doped with the semiconductor of the first conductivity type and the source region 21 doped with the semiconductor of the second conductivity type. The width ratio of the base region 22 doped with the first conductivity type to the source region 21 doped with the second conductivity type is 1:1-3. For specific applications, values ​​such as 1:1; 1:2; 1:3; 1:1.5; 1:2.8 can be selected.

[0053] Precisely controlling the effective channel length of the MOSFET does not change due to the introduction of the semi-insulating region 222, ensuring that parameters such as the threshold voltage, on-resistance, transconductance, and output characteristics of the MOSFET do not change due to the introduction of the semi-insulating ...

Embodiment 3

[0055] The MOSFET containing the semi-insulating region of this embodiment, such as figure 2 As shown, a further improvement is made on the basis of Embodiments 1 and 2, and the depth of the semiconductor-doped base region 22 is consistent with that of the second conductivity type semiconductor-doped source region 21 . Ensure that the channel carriers are transported smoothly without "crossing the ridge", otherwise the formed abrupt junction will form a potential barrier for the carriers, which is not conducive to the normal operation of the device.

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Abstract

The invention discloses an MOSFET (metal oxide semiconductor field effect transistor) with a semi-insulating region and a preparation method thereof and belongs to the technical field of high-voltageelectronics and power. The MOSFET with the semi-insulating region is characterized in that the semi-insulating region is positioned below a first conductive-type semiconductor-doped base region and asecond conductive-type semiconductor-doped transmitting region which are arranged side by side; both the bottom and lateral side of the semi-insulating region are in contact with a second conductive-type semiconductor-doped drift layer; the semi-insulating region is formed by: performing ion implantation on second conductive-type impurities to arrive at contra-doping so as to form an electrical neutral layer, performing ion implantation on amphoteric impurity elements to form a semi-insulating region, and performing ion implantation on first conductive-type impurities above the semi-insulatingregion to form a shallow base region. By narrowing a region of MOSFET parasitic transistors, the problem is solved that startup of conventional MOSFET parasitic transistors cause uncontrollable current under UIS condition, causing 'heat rush'; avalanche tolerance, robustness, high current resistance, breakthrough voltage and reliability can be significantly improved.

Description

technical field [0001] The invention relates to the technical field of high-voltage power electronics, relates to a semiconductor power device, in particular to a MOSFET containing a semi-insulating region and a preparation method thereof. Background technique [0002] With the continuous improvement of the performance requirements of power conversion devices, higher requirements are put forward for power MOS transistor devices that undertake power conversion functions, one of which is to have high avalanche tolerance in the unclamped inductive load switching process (UIS) , that is, it has a high ability to resist UIS avalanche breakdown. This is because the energy stored in the inductive load under UIS conditions is required to be fully released by the power MOS transistor when it is turned off. At this time, the high current stress in the circuit is very high. It is easy to cause device failure, so the level of avalanche breakdown resistance is one of the important indica...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0619H01L29/66712H01L29/7802H01L29/66068H01L29/1608H01L29/167H01L29/0653H01L29/1095
Inventor 周郁明王兵
Owner ANHUI UNIVERSITY OF TECHNOLOGY
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