Single ended bitline current sense amplifier for SRAM applications

Abstract

Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein the read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in an input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage leveloutput signal when the low current level value is detected.

Description

Background technique [0001] The present invention relates generally to current sense sense amplifiers, memory circuits including the same, and more particularly to processors including memory circuits and methods for amplifying data signals on bit lines. [0002] Integrated circuits are used in a variety of electronic applications, from simple devices such as watches to the most complex computer systems. Low power circuits are becoming more common due to the desire to reduce power consumption. In particular, power consumption has become a limiting factor in the yield of high-performance circuit designs (operating at 1 GHz and above) fabricated in deep submicron technologies. Low power designs are also preferred as they exhibit less power supply noise and offer better tolerance to manufacturing variations. Also, users demand larger and faster memories, which increases power consumption. [0003] In a semiconductor memory device such as a dynamic random access memory (DRAM) o...

AI Technical Summary

Problems solved by technology

The increase in density leads to an increase in the load capacitance on the data lines, which reduces the readout speed of the memory device

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