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Transverse power device with mixed conductive pattern and preparation method thereof

A lateral power device and mode technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reduced device loss characteristics, low on-voltage drop, long off-time, etc. Turn-on voltage drop, improved breakdown voltage, and low turn-off loss

Active Publication Date: 2018-03-09
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the LIGBT device is turned on, due to the conductance modulation effect in the drift region, a low turn-on voltage drop can be obtained, but when it is turned off, due to the existence of a large number of unbalanced carriers stored in the drift region, the turn-off time is long, Large turn-off loss
At the same time, due to the existence of the PN junction in the collector area of ​​the device, when the device is conducting forward, in the low collector voltage region, and at the same current density, the conduction voltage drop of LIGBT is larger than that of LDMOS devices, which is not conducive to the reduction of device loss characteristics. Small

Method used

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  • Transverse power device with mixed conductive pattern and preparation method thereof
  • Transverse power device with mixed conductive pattern and preparation method thereof
  • Transverse power device with mixed conductive pattern and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] Such as figure 2 , image 3 As shown, a lateral power device with a mixed conduction mode includes a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 arranged sequentially from bottom to top; one end of the N-type drift region 3 is provided with a P Type base area 4, the other end is provided with N-type buffer area 8; Described P-type base area 4 inner top is provided with N-type source area 5 and P-type contact area 6, and described N-type buffer area 8 inner top is provided with P type collector region 9; emitter 10 above the P-type contact region 6 and part of the N-type source region 5; part of the upper surface of the P-type collector region 9 has a collector electrode 12; above the P-type base region 4 A gate dielectric layer 7 is also provided, and a gate electrode 11 is arranged above the gate dielectric layer 7. The length of the gate structure formed by the gate dielectric layer 7 and the gate electrode 11 is greater than the length ...

Embodiment 2

[0049] Such as Figure 4 As shown, the difference between this example and Example 1 is that the N-type drift region 3 is composed of a first doped region 31 and a second doped region 32 whose concentration increases from left to right. Compared with Embodiment 1, this embodiment can further increase the breakdown voltage of the device, increase the turn-off speed of the device, and reduce the turn-off loss.

Embodiment 3

[0051] Such as Figure 5 As shown, the difference between this example and Example 1 is that there is a P-type RESURF buried layer 18 under the dielectric buried layer 16 in the N-type drift region 3 . The depth of the P-type RESURF buried layer from the dielectric buried layer 16 is 1-4 microns, and the thickness is 0.5-2 microns. Compared with Example 1, through the 3-dimensional RESURF effect of the P-type RESURF buried layer and the 3-dimensional expansion of the depletion layer, this embodiment can further increase the breakdown voltage of the device, and at the same time further increase the turn-off speed of the device, reducing turn-off loss.

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PUM

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Abstract

The invention provides a transverse power device with a mixed conductive pattern and a preparation method thereof. The transverse power device includes a P-type liner, a buried oxidation layer, an N-type drift area, a P-type basic area, an N-type buffer area, an N-type source area, a P-type contact area, a P-type collecting electrode area, an emitting electrode, a collecting electrode, a gate medium layer and a gate electrode; the surface of the N-type drift area is provided with N-type strips and P-type strips, the N-type strips and the P-type strips are arrayed on the surface of the drift area of the device body in the direction perpendicular to the length direction of a gutter alternatively, and the drift area below the N-type strips and the P-type strips is internally provided with a medium burying layer; medium groove structures are arranged among the N-type strips, the P-type strips, the medium burying layer and the N-type buffer area; the concentration of the N-type strips and the P-type strips is higher than that of the N-type drift area. According to the transverse power device, mixed conduction of an SJ-LDMOS and an LIGBT at the surface is achieved, a lower conduction voltage drop, a higher endurable voltage, higher switch-on and switch-off speed and lower switch-off loss can be obtained, a snapback effect is eliminated, and the performance of the device is greatly improved.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a lateral power semiconductor device with a mixed conduction mode and a preparation method thereof. Background technique [0002] Lateral Insulated Gate Bipolar Transistor (LIGBT) is a lateral power device that combines the advantages of lateral power MOSFETs and bipolar transistors, and has the characteristics of high input impedance and reduced conduction voltage. , are widely used in various power integrated circuits. Compared with traditional devices based on bulk silicon technology, devices manufactured using SOI technology have many advantages such as fast speed, low power consumption, high integration density, strong anti-latch ability, low cost, and good radiation resistance. Therefore, LIGBT devices based on SOI materials also have the advantages of good insulation performance, low substrate leakage current, small parasitic capacitance an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L29/06H01L29/36H01L21/331
CPCH01L29/0634H01L29/36H01L29/6625H01L29/66325H01L29/7393
Inventor 张金平彭鑫刘竞秀李泽宏任敏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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