Convolutional neural network calculation instruction and method thereof

Abstract

The invention provides a convolutional neural network calculation instruction and a method thereof. The convolutional neural network calculation instruction comprises at least one operation code and at least one operation domain, wherein the operation codes are used for indicating a function of the convolutional neural network calculation instruction; the operation domains are used for indicatingdata information of the convolutional neural network calculation instruction; and the data information comprises an immediate operand or a register number, and specifically comprises an initial address and the data length of input data, an initial address and the data length of a convolution kernel, and the type of an activation function. Output data serves as input data of the next layer.

Description

technical field [0001] The present disclosure generally relates to artificial neural networks, and specifically relates to a convolutional neural network operation instruction and a method thereof. Background technique [0002] Convolutional neural network is an efficient recognition algorithm widely used in pattern recognition, image processing and other fields in recent years. It has the characteristics of simple structure, few training parameters and strong adaptability, translation, rotation and scaling. Since the feature detection layer of CNN / DNN learns through training data, when using CNN / DNN, it avoids explicit feature extraction and learns implicitly from training data; The weights of the cells are the same, so the network can learn in parallel, which is also a big advantage of the convolutional network over the network of neurons connected to each other. [0003] In existing computer field applications, applications related to convolution operations are very comm...

AI Technical Summary

Problems solved by technology

[0007] The purpose of this disclosure is to provide a device supporting convolutional neural network, which solves the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, etc.

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