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Network and hierarchical routing constructs with heterogeneous memory structures for scalable event-driven computing systems

A driver and event technology, applied in transmission systems, biological neural network models, electrical components, etc., can solve problems such as limiting the space of network connection solutions, maximize network programmability or/and flexibility, minimize memory requirements or / and delayed effects

Active Publication Date: 2022-01-28
UNIV ZURICH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Current large-scale mimetic computing either optimizes bandwidth usage while minimizing power consumption and latency, which limits the space for networking solutions such as Neurogrid; or uses large amounts of storage to maximize flexibility and programmability resources, silicon area, power consumption, such as SpiNNaker

Method used

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  • Network and hierarchical routing constructs with heterogeneous memory structures for scalable event-driven computing systems
  • Network and hierarchical routing constructs with heterogeneous memory structures for scalable event-driven computing systems
  • Network and hierarchical routing constructs with heterogeneous memory structures for scalable event-driven computing systems

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Embodiment Construction

[0064] Embodiments of the present invention provide a VLSI (Very Large Scale Integration, Very Large Scale Integration) with a distributed memory and a heterogeneous memory structure for a scalable neural network, which can implement an event-driven neural architecture. The hierarchical router architecture provides a power and time efficient strategy for interconnecting nodes within and between multiple cores distributed on a multicore chip. Distributed memory in the cores and events broadcast in each core provide a large fan-out to enable large neural networks with structural constraints typical of biologically possible models. Fully asynchronous router and programming constructs allow fast operations of synaptic computations for upcoming offline learning.

[0065] The terms neuron and synapse as used herein represent electrical circuits that mimic biological neurons and synapses. Electronic neurons sum up the contributions of associated synapses to generate spike events. N...

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Abstract

The present invention relates to a very large scale integrated circuit (VLSI) and its routing architecture. In order to solve the transmission control problem of managing asynchronous events in such a large-scale system, it includes multiple interconnected core circuits arranged on multiple tiles, using a local first router for providing intra-core connectivity and / or passing events to an intermediate-level second router for inter-core connectivity and a higher-level third router for inter-cell connectivity; and for parallel A broadcast driver that broadcasts incoming events to all memory circuits in the core circuit. The present invention achieves the technical effect of minimizing memory requirements and delay, but maximizing programming flexibility to support a wide range of event-based neural network architectures.

Description

technical field [0001] The invention relates to a very large scale integrated circuit (VLSI), in particular to an event-based routing network combining a layered routing structure and a heterogeneous memory architecture. Background technique [0002] Included in neuromorphic computing systems are networks of neurons, which use asynchronous events in both computation and communication. Such computing systems have many advantages in terms of bandwidth and power consumption. But managing the traffic of asynchronous events in such large-scale systems is frustrating in terms of circuit complexity and memory requirements. The bottlenecks in building massively configurable mimetic computing platforms are bandwidth, latency, and storage requirements for routing address-events between neurons. Current large-scale mimetic computing either optimizes bandwidth usage while minimizing power consumption and latency, which limits the space for networking solutions such as Neurogrid; or us...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/049G06N3/063H04L45/04H04L49/25
Inventor 贾科莫·因迪维利萨博·莫拉蒂乔宁法比奥·斯帝芬尼
Owner UNIV ZURICH
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