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A wafer-level fan-out stack packaging process method

A packaging process and fan-out technology, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of high manufacturing cost and complicated process, and achieve the effects of saving material costs, reducing manufacturing costs, and reducing packaging manufacturing costs

Active Publication Date: 2019-08-20
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defects of high manufacturing cost and complicated process of fan-out stack packaging in the prior art, thereby providing a wafer-level fan-out stack packaging process method

Method used

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  • A wafer-level fan-out stack packaging process method
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  • A wafer-level fan-out stack packaging process method

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Embodiment 1

[0039]Embodiment 1 provides a wafer-level fan-out stack packaging process method, such as figure 1 As shown, it includes the following steps:

[0040] Step S1: Paste a layer of dry photoresist film 3 on the high-temperature bonding adhesive layer 2 on the light-transmitting temporary substrate 1 . The high-temperature bonding adhesive layer 2 can be cured at a lower temperature and has a stronger adhesive force. When the material is heated to a higher temperature, such as higher than 300°C, the interface between it and the light-transmitting temporary substrate 1 Can lose stickiness. The total thickness of the high-temperature bonding adhesive layer 2 is generally less than 10 μm. The high-temperature bonding adhesive layer 2 can be attached to the surface of the light-transmitting temporary substrate 1 by means of spray coating, spin coating, or film sticking. A layer of dry photoresist film 3 is pasted on the surface of the high-temperature bonding adhesive layer 2, and t...

Embodiment 2

[0055] Embodiment 2 provides a process method of wafer-level fan-out stack packaging, which includes all the steps of embodiment 1, and will not be repeated here to avoid repetition. Embodiment 2 discloses a specific method for stacking more than two packaging units to obtain a fan-out stacked packaging structure, that is, using the micro-bumps of the rewiring layer on the upper packaging unit 21 to interfere with the solidification on the lower packaging unit 22 adjacent to it. The conductive metal pillars exposed on the final dry photoresist film to realize the stacking of package units, such as Figure 13 shown.

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Abstract

A wafer-level fan-out stack packaging process method, comprising the steps of: attaching a layer of dry photoresist film on the high-temperature bonding adhesive layer on the light-transmitting temporary substrate; forming a dry photoresist film on the dry photoresist film A plurality of blind holes directly through the high-temperature bonding adhesive layer; after the dry photoresist film is cured, implant conductive metal posts in the blind holes; mount bare chips on the surface of the dry photoresist film; the overall Injection molding and grinding the surface of the plastic package until the pads of the bare chip are completely exposed; making a rewiring layer on the grinding surface of the plastic package for connecting the conductive metal post and the bare chip, so The rewiring layer is provided with micro-bumps obtained by ball planting and reflow soldering; the light-transmitting temporary substrate and the high-temperature bonding adhesive layer are removed to obtain a packaging unit; a fan-out stacked packaging structure is obtained according to the packaging unit. The invention simplifies the manufacturing process of the fan-out stacked packaging and reduces the manufacturing cost of the stacked packaging.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level fan-out stack packaging process method. Background technique [0002] With the increasing integration of electronic devices, a stacked semiconductor packaging technology (Package on Package, PoP for short) and a stacked die package technology (Stacked Die Package) have been proposed in the field of semiconductor packaging. In this type of package, multiple packages or bare chips are overlapped in the height direction to reduce the footprint of the package. [0003] At present, the chip stacking PoP commonly used mostly adopts the packaging method of wire bond or flip chip (Flip chip) on the redistribution substrate. First, reserve pads or holes through the plastic film on the bottom substrate, and then use wire bond (WB for short) or Flip-Chip (FC for short) or a combination of the two to package the chip on the upper layer. The method realizes the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L21/60
CPCH01L21/56H01L24/64H01L21/568H01L2224/04105H01L2224/12105H01L2224/19H01L2224/32225H01L2224/48235H01L2224/73265H01L2224/73267H01L2224/92244
Inventor 姚大平宋涛
Owner NAT CENT FOR ADVANCED PACKAGING
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