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A Low Noise and Low Loss Insulated Gate Bipolar Transistor

A bipolar transistor, low-loss technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., to reduce noise and speed up turn-on

Active Publication Date: 2020-01-07
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these high-power, high-switching-frequency devices bring convenience to people, but also have negative impacts

Method used

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  • A Low Noise and Low Loss Insulated Gate Bipolar Transistor
  • A Low Noise and Low Loss Insulated Gate Bipolar Transistor
  • A Low Noise and Low Loss Insulated Gate Bipolar Transistor

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Embodiment 1

[0030] Combine below Figure 3-4 , to describe the present invention in detail, a low-noise and low-loss insulated gate bipolar transistor, comprising: a P-type substrate 1, an anode metal layer is arranged at the bottom of the P-type substrate 1 and serves as the collector of the device, An N-type buffer layer 2 is arranged above the P-type substrate 1, an N-type epitaxial layer 3 is arranged on the N-type buffer layer 2, and a P-type body region 9 distributed in a one-dimensional array is arranged in the N-type epitaxial layer 3, On both sides of the part of the N-type epitaxial layer between adjacent P-type body regions 9, heavily doped N-type emitter regions 10 are respectively provided, and the heavily doped N-type emitter regions are located in the corresponding P-type body regions 9, It is characterized in that the transistor also includes trenches whose sidewalls are distributed in a one-dimensional array and covered with an isolation oxide layer 8, and each trench tra...

Embodiment 2

[0032] A method for preparing a low-noise and low-loss insulated gate bipolar transistor, comprising:

[0033] The first step: first select N-type silicon material as the substrate and epitaxially grow shallowly doped N-type epitaxial layer;

[0034] The second step: ion implantation of N-type impurities, and annealing to form a lightly doped N-type carrier storage layer 13;

[0035] Step 3: etching the trench and forming an isolation oxide layer 8;

[0036] The fourth step: ion implantation of P-type impurities, and annealing to form P-type body region 9;

[0037] Step 5: The ion implantation dose range at the bottom of the trench is 1e13cm -2 to 1e18cm -2 , P-type impurities with an energy of 80Kev, and annealed to form a heavily doped P well 4;

[0038] Step 6: Deposit metal in the trench to form a metal connection layer-51;

[0039] Step 7: Deposit polysilicon in the trench, and the ion implantation dose is greater than 1e17cm -2 The P-type impurities form the diode ...

Embodiment 3

[0049] A low-noise and low-loss insulated gate bipolar transistor, comprising: a P-type substrate 1, an anode metal layer is provided at the bottom of the P-type substrate 1 and serves as a collector of the device, above the P-type substrate 1 An N-type buffer layer 2 is provided, an N-type epitaxial layer 3 is arranged on the N-type buffer layer 2, and a P-type body region 9 distributed in a one-dimensional array is arranged in the N-type epitaxial layer 3. Both sides of the part of the N-type epitaxial layer between the regions 9 are respectively provided with heavily doped N-type emitter regions 10, and the heavily doped N-type emitter regions are located in the corresponding P-type body regions 9, refer to Figure 15 , the transistor also includes trenches whose sidewalls are distributed in a one-dimensional array and covered with an isolation oxide layer 8, and each trench traverses through each P-type body region 9, heavily doped N-type emitter region 10 and N-type epitax...

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Abstract

The invention relates to a low-noise low-loss insulated gate bipolar transistor. The low-noise low-loss insulated gate bipolar transistor comprises a P-type substrate of which the bottom is provided with a collector metal electrode; an N-type buffer layer is arranged on the P-type substrate; an N-type epitaxial layer is arranged on the N-type buffer layer; one-dimensional arrayed P-type body regions are arranged in the N-type epitaxial layer; heavily doped N-type emission regions are arranged in the P-type body regions; N type carrier storage layers are arranged between the P-type body regions and the N-type epitaxial layer; the transistor further comprises one-dimensional arrayed trenches of which the sidewalls are coated with isolated oxide layers; the trenches transversely penetrate the P-type body regions, the heavily doped N-type emission regions and the N-type epitaxial layer; diodes connected with metal layers are arranged in the trenches; heavily doped P wells are formed below the trenches; gate oxide layers are arranged above the N-type epitaxial layer between adjacent trenches; the upper parts of the gate oxide layers are covered with polycrystalline silicon gates; and the heavily doped N-type emission regions and the P-type body regions are connected with second connecting layers, so that the emitters of the device can be formed.

Description

technical field [0001] The invention mainly relates to the technical field of power semiconductor devices, in particular to a low-noise and low-loss insulated gate bipolar transistor, which is especially suitable for high-power systems such as intelligent power modules, new energy electric vehicle motor drive systems, and electric welding machines. Background technique [0002] Insulated Gate Bipolar Transistor (IGBT) is a composite power device evolved from the combination of MOS gate device structure and bipolar transistor structure. It has the characteristics of both MOS transistor and bipolar transistor, and has good on-state current and The trade-off relationship between switching losses. Compared with other types of power devices, IGBT has the advantages of high forward conduction current density and low conduction voltage drop, simple drive circuit, good controllability, and large safe operating area. After more than thirty years of development and research, IGBT tec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L21/331
CPCH01L29/66348H01L29/7397
Inventor 孙伟锋李胜徐志远杨卓张小双刘斯扬陆生礼时龙兴
Owner SOUTHEAST UNIV
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